| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pci/ |
| nouveau_nvkm_subdev_pci_g84.c | 88 u32 mask_value; local in function:g84_pcie_set_link_speed
91 mask_value = 0x20;
93 mask_value = 0x10;
95 nvkm_pci_mask(pci, 0x460, 0x30, mask_value);
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| nouveau_nvkm_subdev_pci_g84.c | 88 u32 mask_value; local in function:g84_pcie_set_link_speed
91 mask_value = 0x20;
93 mask_value = 0x10;
95 nvkm_pci_mask(pci, 0x460, 0x30, mask_value);
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| nouveau_nvkm_subdev_pci_gk104.c | 135 u32 mask_value; local in function:gk104_pcie_set_link_speed
139 mask_value = 0x00000;
142 mask_value = 0x40000;
146 mask_value = 0x80000;
150 nvkm_mask(device, 0x8c040, 0xc0000, mask_value);
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| nouveau_nvkm_subdev_pci_gk104.c | 135 u32 mask_value; local in function:gk104_pcie_set_link_speed
139 mask_value = 0x00000;
142 mask_value = 0x40000;
146 mask_value = 0x80000;
150 nvkm_mask(device, 0x8c040, 0xc0000, mask_value);
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| mmsch_v1_0.h | 83 uint32_t mask_value; member in struct:mmsch_v1_0_cmd_direct_read_modify_write
88 uint32_t mask_value; member in struct:mmsch_v1_0_cmd_direct_polling
117 direct_rd_mod_wt->mask_value = mask;
129 direct_poll->mask_value = mask;
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| mmsch_v1_0.h | 83 uint32_t mask_value; member in struct:mmsch_v1_0_cmd_direct_read_modify_write
88 uint32_t mask_value; member in struct:mmsch_v1_0_cmd_direct_polling
117 direct_rd_mod_wt->mask_value = mask;
129 direct_poll->mask_value = mask;
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| /src/sys/external/bsd/ena-com/ |
| ena_com.c | 1625 u32 mask_value = 0; local in function:ena_com_set_admin_polling_mode
1628 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1630 ENA_REG_WRITE32(ena_dev->bus, mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
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| ena_com.c | 1625 u32 mask_value = 0; local in function:ena_com_set_admin_polling_mode
1628 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1630 ENA_REG_WRITE32(ena_dev->bus, mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ci_dpm.c | 2619 u32 mask_value = 0; local in function:ci_get_dpm_level_enable_mask_value
2622 mask_value = mask_value << 1;
2624 mask_value |= 0x1;
2626 mask_value &= 0xFFFFFFFE;
2629 return mask_value;
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| radeon_ci_dpm.c | 2619 u32 mask_value = 0; local in function:ci_get_dpm_level_enable_mask_value
2622 mask_value = mask_value << 1;
2624 mask_value |= 0x1;
2626 mask_value &= 0xFFFFFFFE;
2629 return mask_value;
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