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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_dmcu.c 178 union dce_dmcu_psr_config_data_reg1 masterCmdData1;
239 masterCmdData1.u32All = 0;
240 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
241 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
242 masterCmdData1.bits.rfb_update_auto_en =
244 masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
245 masterCmdData1.bits.dcp_sel = psr_context->controllerId;
246 masterCmdData1.bits.phy_type = psr_context->phyType;
247 masterCmdData1.bits.frame_cap_ind =
249 masterCmdData1.bits.aux_chan = psr_context->channel
    [all...]
amdgpu_dce_dmcu.c 178 union dce_dmcu_psr_config_data_reg1 masterCmdData1;
239 masterCmdData1.u32All = 0;
240 masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
241 masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
242 masterCmdData1.bits.rfb_update_auto_en =
244 masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
245 masterCmdData1.bits.dcp_sel = psr_context->controllerId;
246 masterCmdData1.bits.phy_type = psr_context->phyType;
247 masterCmdData1.bits.frame_cap_ind =
249 masterCmdData1.bits.aux_chan = psr_context->channel
    [all...]

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