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Searched defs:mec_int_cntl (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c	`4856 u32 mec_int_cntl, mec_int_cntl_reg; local in function:gfx_v10_0_set_compute_eop_interrupt_state 4889 mec_int_cntl = RREG32(mec_int_cntl_reg); 4890 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4892 WREG32(mec_int_cntl_reg, mec_int_cntl); 4895 mec_int_cntl = RREG32(mec_int_cntl_reg); 4896 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4898 WREG32(mec_int_cntl_reg, mec_int_cntl);`
amdgpu_gfx_v7_0.c	`4736 u32 mec_int_cntl, mec_int_cntl_reg; local in function:gfx_v7_0_set_compute_eop_interrupt_state 4769 mec_int_cntl = RREG32(mec_int_cntl_reg); 4770 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4771 WREG32(mec_int_cntl_reg, mec_int_cntl); 4774 mec_int_cntl = RREG32(mec_int_cntl_reg); 4775 mec_int_cntl \|= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4776 WREG32(mec_int_cntl_reg, mec_int_cntl);`
amdgpu_gfx_v10_0.c	`4856 u32 mec_int_cntl, mec_int_cntl_reg; local in function:gfx_v10_0_set_compute_eop_interrupt_state 4889 mec_int_cntl = RREG32(mec_int_cntl_reg); 4890 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4892 WREG32(mec_int_cntl_reg, mec_int_cntl); 4895 mec_int_cntl = RREG32(mec_int_cntl_reg); 4896 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4898 WREG32(mec_int_cntl_reg, mec_int_cntl);`
amdgpu_gfx_v7_0.c	`4736 u32 mec_int_cntl, mec_int_cntl_reg; local in function:gfx_v7_0_set_compute_eop_interrupt_state 4769 mec_int_cntl = RREG32(mec_int_cntl_reg); 4770 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4771 WREG32(mec_int_cntl_reg, mec_int_cntl); 4774 mec_int_cntl = RREG32(mec_int_cntl_reg); 4775 mec_int_cntl \|= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4776 WREG32(mec_int_cntl_reg, mec_int_cntl);`
amdgpu_gfx_v8_0.c	`6521 u32 mec_int_cntl, mec_int_cntl_reg; local in function:gfx_v8_0_set_compute_eop_interrupt_state 6554 mec_int_cntl = RREG32(mec_int_cntl_reg); 6555 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 6556 WREG32(mec_int_cntl_reg, mec_int_cntl); 6559 mec_int_cntl = RREG32(mec_int_cntl_reg); 6560 mec_int_cntl \|= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 6561 WREG32(mec_int_cntl_reg, mec_int_cntl);`
amdgpu_gfx_v8_0.c	`6521 u32 mec_int_cntl, mec_int_cntl_reg; local in function:gfx_v8_0_set_compute_eop_interrupt_state 6554 mec_int_cntl = RREG32(mec_int_cntl_reg); 6555 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 6556 WREG32(mec_int_cntl_reg, mec_int_cntl); 6559 mec_int_cntl = RREG32(mec_int_cntl_reg); 6560 mec_int_cntl \|= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 6561 WREG32(mec_int_cntl_reg, mec_int_cntl);`
amdgpu_gfx_v9_0.c	`5398 u32 mec_int_cntl, mec_int_cntl_reg; local in function:gfx_v9_0_set_compute_eop_interrupt_state 5431 mec_int_cntl = RREG32(mec_int_cntl_reg); 5432 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5434 WREG32(mec_int_cntl_reg, mec_int_cntl); 5437 mec_int_cntl = RREG32(mec_int_cntl_reg); 5438 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5440 WREG32(mec_int_cntl_reg, mec_int_cntl);`
amdgpu_gfx_v9_0.c	`5398 u32 mec_int_cntl, mec_int_cntl_reg; local in function:gfx_v9_0_set_compute_eop_interrupt_state 5431 mec_int_cntl = RREG32(mec_int_cntl_reg); 5432 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5434 WREG32(mec_int_cntl_reg, mec_int_cntl); 5437 mec_int_cntl = RREG32(mec_int_cntl_reg); 5438 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5440 WREG32(mec_int_cntl_reg, mec_int_cntl);`

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