| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_navi10_ppt.c | 1460 struct smu_clocks min_clocks = {0}; local in function:navi10_notify_smc_display_config
1464 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1465 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1466 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1470 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1477 min_clocks.dcef_clock_in_sr/100);
1489 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
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| amdgpu_vega20_ppt.c | 2242 struct smu_clocks min_clocks = {0}; local in function:vega20_notify_smc_display_config
2246 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2247 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2248 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2252 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2257 min_clocks.dcef_clock_in_sr/100);
2269 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
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| amdgpu_navi10_ppt.c | 1460 struct smu_clocks min_clocks = {0}; local in function:navi10_notify_smc_display_config
1464 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1465 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1466 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1470 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1477 min_clocks.dcef_clock_in_sr/100);
1489 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
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| amdgpu_vega20_ppt.c | 2242 struct smu_clocks min_clocks = {0}; local in function:vega20_notify_smc_display_config
2246 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2247 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2248 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2252 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2257 min_clocks.dcef_clock_in_sr/100);
2269 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega12_hwmgr.c | 1481 struct PP_Clocks min_clocks = {0}; local in function:vega12_notify_smc_display_config_after_ps_adjustment
1491 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1492 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1493 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1497 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
1503 min_clocks.dcefClockInSR /100),
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| amdgpu_vega12_hwmgr.c | 1481 struct PP_Clocks min_clocks = {0}; local in function:vega12_notify_smc_display_config_after_ps_adjustment
1491 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1492 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1493 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1497 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
1503 min_clocks.dcefClockInSR /100),
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| amdgpu_vega20_hwmgr.c | 2306 struct PP_Clocks min_clocks = {0}; local in function:vega20_notify_smc_display_config_after_ps_adjustment
2310 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2311 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2312 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2316 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2321 min_clocks.dcefClockInSR / 100)) == 0,
2330 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
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| amdgpu_vega20_hwmgr.c | 2306 struct PP_Clocks min_clocks = {0}; local in function:vega20_notify_smc_display_config_after_ps_adjustment
2310 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2311 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2312 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2316 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2321 min_clocks.dcefClockInSR / 100)) == 0,
2330 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
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| amdgpu_vega10_hwmgr.c | 3974 struct PP_Clocks min_clocks = {0}; local in function:vega10_notify_smc_display_config_after_ps_adjustment
3985 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
3986 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
3987 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3990 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
4000 min_clocks.dcefClockInSR / 100);
4008 if (min_clocks.memoryClock != 0) {
4009 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
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| amdgpu_smu7_hwmgr.c | 3612 struct PP_Clocks min_clocks = {0}; local in function:smu7_find_dpm_states_clocks_in_dpm_table
3629 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3630 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
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| amdgpu_vega10_hwmgr.c | 3974 struct PP_Clocks min_clocks = {0}; local in function:vega10_notify_smc_display_config_after_ps_adjustment
3985 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
3986 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
3987 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3990 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
4000 min_clocks.dcefClockInSR / 100);
4008 if (min_clocks.memoryClock != 0) {
4009 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
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| amdgpu_smu7_hwmgr.c | 3612 struct PP_Clocks min_clocks = {0}; local in function:smu7_find_dpm_states_clocks_in_dpm_table
3629 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3630 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
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