| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_arcturus_ppt.c | 377 uint32_t i, num_of_levels = 0, clk; local in function:arcturus_set_single_dpm_table
387 smu_read_smc_arg(smu, &num_of_levels);
388 if (!num_of_levels) {
393 single_dpm_table->count = num_of_levels;
394 for (i = 0; i < num_of_levels; i++) {
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| amdgpu_vega20_ppt.c | 676 uint32_t i, num_of_levels = 0, clk; local in function:vega20_set_single_dpm_table
686 smu_read_smc_arg(smu, &num_of_levels);
687 if (!num_of_levels) {
692 single_dpm_table->count = num_of_levels;
694 for (i = 0; i < num_of_levels; i++) {
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| amdgpu_arcturus_ppt.c | 377 uint32_t i, num_of_levels = 0, clk; local in function:arcturus_set_single_dpm_table
387 smu_read_smc_arg(smu, &num_of_levels);
388 if (!num_of_levels) {
393 single_dpm_table->count = num_of_levels;
394 for (i = 0; i < num_of_levels; i++) {
|
| amdgpu_vega20_ppt.c | 676 uint32_t i, num_of_levels = 0, clk; local in function:vega20_set_single_dpm_table
686 smu_read_smc_arg(smu, &num_of_levels);
687 if (!num_of_levels) {
692 single_dpm_table->count = num_of_levels;
694 for (i = 0; i < num_of_levels; i++) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega12_hwmgr.c | 487 PPCLK_e clk_id, uint32_t *num_of_levels)
498 *num_of_levels = smum_get_argument(hwmgr);
499 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
527 uint32_t i, num_of_levels, clk; local in function:vega12_setup_single_dpm_table
529 ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
534 dpm_table->count = num_of_levels;
536 for (i = 0; i < num_of_levels; i++) {
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| amdgpu_vega12_hwmgr.c | 487 PPCLK_e clk_id, uint32_t *num_of_levels)
498 *num_of_levels = smum_get_argument(hwmgr);
499 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
527 uint32_t i, num_of_levels, clk; local in function:vega12_setup_single_dpm_table
529 ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
534 dpm_table->count = num_of_levels;
536 for (i = 0; i < num_of_levels; i++) {
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| amdgpu_vega20_hwmgr.c | 530 PPCLK_e clk_id, uint32_t *num_of_levels)
541 *num_of_levels = smum_get_argument(hwmgr);
542 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
573 uint32_t i, num_of_levels, clk; local in function:vega20_setup_single_dpm_table
575 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
580 dpm_table->count = num_of_levels;
582 for (i = 0; i < num_of_levels; i++) {
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| amdgpu_vega20_hwmgr.c | 530 PPCLK_e clk_id, uint32_t *num_of_levels)
541 *num_of_levels = smum_get_argument(hwmgr);
542 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
573 uint32_t i, num_of_levels, clk; local in function:vega20_setup_single_dpm_table
575 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
580 dpm_table->count = num_of_levels;
582 for (i = 0; i < num_of_levels; i++) {
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