| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/ |
| jh7100-beaglev-starlight.dts | 16 phy-handle = <&phy>;
20 phy: ethernet-phy@7 { label
|
| jh7100-starfive-visionfive-v1.dts | 22 phy-handle = <&phy>;
26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
32 * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
36 phy: ethernet-phy@0 { label
|
| jh7100-beaglev-starlight.dts | 16 phy-handle = <&phy>;
20 phy: ethernet-phy@7 { label
|
| jh7100-starfive-visionfive-v1.dts | 22 phy-handle = <&phy>;
26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
32 * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
36 phy: ethernet-phy@0 { label
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| rk3228-evb.dts | 20 vcc_phy: vcc-phy-regulator {
43 phy-supply = <&vcc_phy>;
44 phy-mode = "rmii";
45 phy-handle = <&phy>;
53 phy: ethernet-phy@0 { label
54 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
58 phy-is-integrated
[all...] |
| rk3228-evb.dts | 20 vcc_phy: vcc-phy-regulator {
43 phy-supply = <&vcc_phy>;
44 phy-mode = "rmii";
45 phy-handle = <&phy>;
53 phy: ethernet-phy@0 { label
54 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
58 phy-is-integrated
[all...] |
| zynq-ebaz4205.dts | 34 phy-mode = "mii";
35 phy-handle = <&phy>;
37 /* PHY clock */
41 phy: ethernet-phy@0 { label
|
| zynq-ebaz4205.dts | 34 phy-mode = "mii";
35 phy-handle = <&phy>;
37 /* PHY clock */
41 phy: ethernet-phy@0 { label
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/ |
| tegra194-p3668.dtsi | 31 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(R, 1) GPIO_ACTIVE_LOW>;
32 phy-handle = <&phy>;
33 phy-mode = "rgmii-id";
39 phy: phy@0 { label
40 compatible = "ethernet-phy-ieee802.3-c22";
44 #phy-cells = <0>;
|
| tegra194-p3668.dtsi | 31 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(R, 1) GPIO_ACTIVE_LOW>;
32 phy-handle = <&phy>;
33 phy-mode = "rgmii-id";
39 phy: phy@0 { label
40 compatible = "ethernet-phy-ieee802.3-c22";
44 #phy-cells = <0>;
|
| tegra186-p3310.dtsi | 38 phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
40 phy-handle = <&phy>;
41 phy-mode = "rgmii";
47 phy: phy@0 { label
48 compatible = "ethernet-phy-ieee802.3-c22";
54 #phy-cells = <0>;
|
| tegra194-p2888.dtsi | 34 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
35 phy-handle = <&phy>;
36 phy-mode = "rgmii-id";
42 phy: phy@0 { label
43 compatible = "ethernet-phy-ieee802.3-c22";
47 #phy-cells = <0>;
|
| tegra186-p3310.dtsi | 38 phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
40 phy-handle = <&phy>;
41 phy-mode = "rgmii";
47 phy: phy@0 { label
48 compatible = "ethernet-phy-ieee802.3-c22";
54 #phy-cells = <0>;
|
| /src/sys/dev/pci/igc/ |
| igc_base.c | 19 * igc_acquire_phy_base - Acquire rights to access PHY
22 * Acquire access rights to the correct PHY.
38 * igc_release_phy_base - Release rights to access PHY
41 * A wrapper to release access rights to the correct PHY.
98 * igc_power_down_phy_copper_base - Remove link during PHY power down
101 * In the case of a PHY power down to save power, or to turn off link during a
107 struct igc_phy_info *phy = &hw->phy; local in function:igc_power_down_phy_copper_base
109 if (!(phy->ops.check_reset_block))
113 if (phy->ops.check_reset_block(hw)
[all...] |
| igc_base.c | 19 * igc_acquire_phy_base - Acquire rights to access PHY
22 * Acquire access rights to the correct PHY.
38 * igc_release_phy_base - Release rights to access PHY
41 * A wrapper to release access rights to the correct PHY.
98 * igc_power_down_phy_copper_base - Remove link during PHY power down
101 * In the case of a PHY power down to save power, or to turn off link during a
107 struct igc_phy_info *phy = &hw->phy; local in function:igc_power_down_phy_copper_base
109 if (!(phy->ops.check_reset_block))
113 if (phy->ops.check_reset_block(hw)
[all...] |
| /src/sys/arch/arm/samsung/ |
| exynos_ehci.c | 74 struct fdtbus_phy *phy; local in function:exynos_ehci_attach
96 phy = fdtbus_phy_get_index(child, 0);
97 if (phy && fdtbus_phy_enable(phy, true) != 0)
98 aprint_error(": couldn't enable phy for %s\n",
|
| exynos_ohci.c | 74 struct fdtbus_phy *phy; local in function:exynos_ohci_attach
96 phy = fdtbus_phy_get_index(child, 0);
97 if (phy && fdtbus_phy_enable(phy, true) != 0)
98 aprint_error(": couldn't enable phy for %s\n",
|
| exynos_ehci.c | 74 struct fdtbus_phy *phy; local in function:exynos_ehci_attach
96 phy = fdtbus_phy_get_index(child, 0);
97 if (phy && fdtbus_phy_enable(phy, true) != 0)
98 aprint_error(": couldn't enable phy for %s\n",
|
| exynos_ohci.c | 74 struct fdtbus_phy *phy; local in function:exynos_ohci_attach
96 phy = fdtbus_phy_get_index(child, 0);
97 if (phy && fdtbus_phy_enable(phy, true) != 0)
98 aprint_error(": couldn't enable phy for %s\n",
|
| /src/sys/arch/arm/ti/ |
| ti_ehci.c | 77 struct fdtbus_phy *phy; local in function:ti_ehci_attach
124 phy = fdtbus_phy_get_index(phandle, n);
125 if (phy && fdtbus_phy_enable(phy, true) != 0) {
126 aprint_error(": couldn't enable phy\n");
|
| ti_ehci.c | 77 struct fdtbus_phy *phy; local in function:ti_ehci_attach
124 phy = fdtbus_phy_get_index(phandle, n);
125 if (phy && fdtbus_phy_enable(phy, true) != 0) {
126 aprint_error(": couldn't enable phy\n");
|
| /src/sys/dev/fdt/ |
| ehci_fdt.c | 75 struct fdtbus_phy *phy; local in function:ehci_fdt_attach
102 /* Enable optional phy */
103 phy = fdtbus_phy_get(phandle, "usb");
104 if (phy && fdtbus_phy_enable(phy, true) != 0) {
105 aprint_error(": couldn't enable phy\n");
|
| ohci_fdt.c | 75 struct fdtbus_phy *phy; local in function:ohci_fdt_attach
102 /* Enable optional phy */
103 phy = fdtbus_phy_get(phandle, "usb");
104 if (phy && fdtbus_phy_enable(phy, true) != 0) {
105 aprint_error(": couldn't enable phy\n");
|
| ehci_fdt.c | 75 struct fdtbus_phy *phy; local in function:ehci_fdt_attach
102 /* Enable optional phy */
103 phy = fdtbus_phy_get(phandle, "usb");
104 if (phy && fdtbus_phy_enable(phy, true) != 0) {
105 aprint_error(": couldn't enable phy\n");
|
| ohci_fdt.c | 75 struct fdtbus_phy *phy; local in function:ohci_fdt_attach
102 /* Enable optional phy */
103 phy = fdtbus_phy_get(phandle, "usb");
104 if (phy && fdtbus_phy_enable(phy, true) != 0) {
105 aprint_error(": couldn't enable phy\n");
|
