| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 434 int pix_clk = 0; local in function:dcn10_get_otg_states
437 pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
462 pix_clk);
|
| amdgpu_dcn10_hw_sequencer_debug.c | 434 int pix_clk = 0; local in function:dcn10_get_otg_states
437 pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
462 pix_clk);
|
| amdgpu_dcn10_hw_sequencer_debug.c | 434 int pix_clk = 0; local in function:dcn10_get_otg_states
437 pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
462 pix_clk);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_resource.c | 1840 uint32_t pix_clk = timing->pix_clk_100hz; local in function:get_norm_pix_clk
1841 uint32_t normalized_pix_clk = pix_clk;
1844 pix_clk /= 2;
1849 normalized_pix_clk = pix_clk;
1852 normalized_pix_clk = (pix_clk * 30) / 24;
1855 normalized_pix_clk = (pix_clk * 36) / 24;
1858 normalized_pix_clk = (pix_clk * 48) / 24;
|
| amdgpu_dc_resource.c | 1840 uint32_t pix_clk = timing->pix_clk_100hz; local in function:get_norm_pix_clk
1841 uint32_t normalized_pix_clk = pix_clk;
1844 pix_clk /= 2;
1849 normalized_pix_clk = pix_clk;
1852 normalized_pix_clk = (pix_clk * 30) / 24;
1855 normalized_pix_clk = (pix_clk * 36) / 24;
1858 normalized_pix_clk = (pix_clk * 48) / 24;
|
| amdgpu_dc_resource.c | 1840 uint32_t pix_clk = timing->pix_clk_100hz; local in function:get_norm_pix_clk
1841 uint32_t normalized_pix_clk = pix_clk;
1844 pix_clk /= 2;
1849 normalized_pix_clk = pix_clk;
1852 normalized_pix_clk = (pix_clk * 30) / 24;
1855 normalized_pix_clk = (pix_clk * 36) / 24;
1858 normalized_pix_clk = (pix_clk * 48) / 24;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_r100.c | 3170 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; local in function:r100_bandwidth_update
3290 pix_clk.full = 0;
3295 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3296 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3298 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3501 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
|
| radeon_r100.c | 3170 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; local in function:r100_bandwidth_update
3290 pix_clk.full = 0;
3295 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3296 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3298 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3501 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
|
| radeon_r100.c | 3170 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; local in function:r100_bandwidth_update
3290 pix_clk.full = 0;
3295 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3296 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3298 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3501 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
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