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Searched defs:pll_cfg3 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/arm/sunxi/
sunxi_hdmiphy.c	`83 #define PLL_CFG3 0x034 196 PHY_READ(sc, PLL_CFG1), PHY_READ(sc, PLL_CFG2), PHY_READ(sc, PLL_CFG3)); 272 uint32_t pll_cfg3; member in struct:sun8i_h3_hdmiphy_init 282 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x8008430a, .pll_cfg3 = 0x1, 288 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x80084343, .pll_cfg3 = 0x1, 294 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x80084381, .pll_cfg3 = 0x1, 299 .pll_cfg1 = 0x35dc5fc0, .pll_cfg2 = 0x800863c0, .pll_cfg3 = 0x1, 335 PHY_WRITE(sc, PLL_CFG3, inittab->pll_cfg3);`
sunxi_hdmiphy.c	`83 #define PLL_CFG3 0x034 196 PHY_READ(sc, PLL_CFG1), PHY_READ(sc, PLL_CFG2), PHY_READ(sc, PLL_CFG3)); 272 uint32_t pll_cfg3; member in struct:sun8i_h3_hdmiphy_init 282 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x8008430a, .pll_cfg3 = 0x1, 288 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x80084343, .pll_cfg3 = 0x1, 294 .pll_cfg1 = 0x3ddc5040, .pll_cfg2 = 0x80084381, .pll_cfg3 = 0x1, 299 .pll_cfg1 = 0x35dc5fc0, .pll_cfg2 = 0x800863c0, .pll_cfg3 = 0x1, 335 PHY_WRITE(sc, PLL_CFG3, inittab->pll_cfg3);`

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