| /src/sys/dev/pci/ |
| ichsmb.c | 274 bus_addr_t sbreg, pmbase; local in function:ichsmb_probe_tco
372 * space. Older manual call this PMBASE for power management;
376 * probably peeks and pokes registers here?) so we say PMBASE
381 pmbase = pci_conf_read(pc, pmc_tag, LPCIB_PCI_PMBASE);
382 aprint_debug_dev(self, "PMBASE=0x%"PRIxBUSADDR"\n", pmbase);
383 if ((pmbase & 1) != 1) { /* I/O space bit? */
388 error = bus_space_map(sc->sc_pmt, PCI_MAPREG_IO_ADDR(pmbase),
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| ichsmb.c | 274 bus_addr_t sbreg, pmbase; local in function:ichsmb_probe_tco
372 * space. Older manual call this PMBASE for power management;
376 * probably peeks and pokes registers here?) so we say PMBASE
381 pmbase = pci_conf_read(pc, pmc_tag, LPCIB_PCI_PMBASE);
382 aprint_debug_dev(self, "PMBASE=0x%"PRIxBUSADDR"\n", pmbase);
383 if ((pmbase & 1) != 1) { /* I/O space bit? */
388 error = bus_space_map(sc->sc_pmt, PCI_MAPREG_IO_ADDR(pmbase),
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| piixpm.c | 510 pcireg_t base, hostc, pmbase; local in function:piixpm_csb5_reset
515 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE);
516 pmbase |= PIIX_PM_BASE_CSB5_RESET;
517 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase);
518 pmbase &= ~PIIX_PM_BASE_CSB5_RESET;
519 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase);
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| piixpm.c | 510 pcireg_t base, hostc, pmbase; local in function:piixpm_csb5_reset
515 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE);
516 pmbase |= PIIX_PM_BASE_CSB5_RESET;
517 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase);
518 pmbase &= ~PIIX_PM_BASE_CSB5_RESET;
519 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase);
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| /src/sys/arch/x86/pci/ |
| ichlpcib.c | 319 pcireg_t pmbase; local in function:lpcibattach
339 * The PMBASE register is alike PCI BAR but not completely compatible
340 * with it. The PMBASE define the base address and the type but
346 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE);
347 if (bus_space_map(sc->sc_pmt, PCI_MAPREG_IO_ADDR(pmbase),
903 * compatible with it. The PMBASE define the base address and the type
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| ichlpcib.c | 319 pcireg_t pmbase; local in function:lpcibattach
339 * The PMBASE register is alike PCI BAR but not completely compatible
340 * with it. The PMBASE define the base address and the type but
346 pmbase = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_PMBASE);
347 if (bus_space_map(sc->sc_pmt, PCI_MAPREG_IO_ADDR(pmbase),
903 * compatible with it. The PMBASE define the base address and the type
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