| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios.h | 51 u32 post_divider; member in struct:atom_clock_dividers
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| amdgpu_atombios.h | 51 u32 post_divider; member in struct:atom_clock_dividers
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rv730_dpm.c | 57 u32 reference_divider, post_divider; local in function:rv730_populate_sclk_value
69 post_divider = ((dividers.post_div >> 4) & 0xf) +
72 post_divider = 1;
74 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
97 u32 vco_freq = engine_clock * post_divider;
136 u32 post_divider, reference_divider; local in function:rv730_populate_mclk_value
147 post_divider = ((dividers.post_div >> 4) & 0xf) +
150 post_divider = 1;
172 u32 vco_freq = memory_clock * post_divider;
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| rv6xx_dpm.h | 36 u32 post_divider; member in struct:rv6xx_sclk_stepping
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| radeon_rv730_dpm.c | 57 u32 reference_divider, post_divider; local in function:rv730_populate_sclk_value
69 post_divider = ((dividers.post_div >> 4) & 0xf) +
72 post_divider = 1;
74 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
97 u32 vco_freq = engine_clock * post_divider;
136 u32 post_divider, reference_divider; local in function:rv730_populate_mclk_value
147 post_divider = ((dividers.post_div >> 4) & 0xf) +
150 post_divider = 1;
172 u32 vco_freq = memory_clock * post_divider;
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| rv6xx_dpm.h | 36 u32 post_divider; member in struct:rv6xx_sclk_stepping
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| radeon_legacy_crtc.c | 758 uint32_t post_divider = 0; local in function:radeon_set_pll
836 &reference_div, &post_divider);
839 if (post_div->divider == post_divider)
850 post_divider);
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| radeon_legacy_crtc.c | 758 uint32_t post_divider = 0; local in function:radeon_set_pll
836 &reference_div, &post_divider);
839 if (post_div->divider == post_divider)
850 post_divider);
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| radeon_rv770_dpm.c | 329 u32 post_divider, reference_divider, feedback_divider8; local in function:rv770_calculate_fractional_mpll_feedback_divider
337 post_divider = dividers->post_div;
341 (8 * fyclk * reference_divider * post_divider) / reference_clock;
506 u32 reference_divider, post_divider; local in function:rv770_populate_sclk_value
518 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2;
520 post_divider = 1;
522 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
544 u32 vco_freq = engine_clock * post_divider;
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| radeon_rv770_dpm.c | 329 u32 post_divider, reference_divider, feedback_divider8; local in function:rv770_calculate_fractional_mpll_feedback_divider
337 post_divider = dividers->post_div;
341 (8 * fyclk * reference_divider * post_divider) / reference_clock;
506 u32 reference_divider, post_divider; local in function:rv770_populate_sclk_value
518 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2;
520 post_divider = 1;
522 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
544 u32 vco_freq = engine_clock * post_divider;
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| radeon_mode.h | 602 u32 post_divider; member in struct:atom_clock_dividers
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| radeon_mode.h | 602 u32 post_divider; member in struct:atom_clock_dividers
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_clock_source.c | 144 uint32_t post_divider,
151 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider;
203 uint32_t post_divider,
216 post_divider,
227 ref_divider * post_divider *
245 pll_settings->pix_clk_post_divider = post_divider;
249 actual_calculated_clock_100hz * post_divider / 10;
265 uint32_t post_divider; local in function:calc_pll_dividers_in_range
276 post_divider = max_post_divider;
277 post_divider >= min_post_divider
[all...] |
| amdgpu_dce_clock_source.c | 144 uint32_t post_divider,
151 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider;
203 uint32_t post_divider,
216 post_divider,
227 ref_divider * post_divider *
245 pll_settings->pix_clk_post_divider = post_divider;
249 actual_calculated_clock_100hz * post_divider / 10;
265 uint32_t post_divider; local in function:calc_pll_dividers_in_range
276 post_divider = max_post_divider;
277 post_divider >= min_post_divider
[all...] |
