| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_pp_smu.c | 256 const struct amd_pp_clocks *pp_clks,
262 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
265 pp_clks->count,
270 dc_clks->num_levels = pp_clks->count;
276 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
277 dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
282 const struct pp_clock_levels_with_latency *pp_clks,
288 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
291 pp_clks->num_levels,
296 clk_level_info->num_levels = pp_clks->num_levels
343 struct amd_pp_clocks pp_clks = { 0 }; local in function:dm_pp_get_clock_levels_by_type
429 struct pp_clock_levels_with_latency pp_clks = { 0 }; local in function:dm_pp_get_clock_levels_by_type_with_latency
[all...] |
| amdgpu_dm_pp_smu.c | 256 const struct amd_pp_clocks *pp_clks,
262 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
265 pp_clks->count,
270 dc_clks->num_levels = pp_clks->count;
276 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
277 dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
282 const struct pp_clock_levels_with_latency *pp_clks,
288 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
291 pp_clks->num_levels,
296 clk_level_info->num_levels = pp_clks->num_levels
343 struct amd_pp_clocks pp_clks = { 0 }; local in function:dm_pp_get_clock_levels_by_type
429 struct pp_clock_levels_with_latency pp_clks = { 0 }; local in function:dm_pp_get_clock_levels_by_type_with_latency
[all...] |
