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  /src/sys/arch/evbsh3/t_sh7706lan/
t_sh7706lan.c 44 uint16_t reg; local
50 reg = _reg_read_2(SH7709_SCPCR);
51 reg &= 0x3ff;
52 _reg_write_2(SH7709_SCPCR, reg);
58 reg = _reg_read_2(SH3_BCR2);
59 reg &= ~(BCR2_AREA_WIDTH_MASK << BCR2_AREA4_SHIFT);
60 reg |= (BCR2_AREA_WIDTH_8 << BCR2_AREA4_SHIFT);
61 _reg_write_2(SH3_BCR2, reg);
  /src/sys/arch/arm/ixp12x0/
ixp12x0.c 49 pcireg_t reg; local
79 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
82 SA_CONTROL, reg);
101 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
104 SA_CONTROL, reg);
133 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
136 SA_CONTROL, reg);
145 reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
151 PCI_COMMAND_STATUS_REG, reg);
  /src/sys/arch/cobalt/stand/boot/
pci.c 42 uint32_t reg; local
49 reg = *pcicfg_data;
52 return reg;
  /src/sys/arch/or1k/include/
reg.h 1 /* $NetBSD: reg.h,v 1.1 2014/09/03 19:34:26 matt Exp $ */
47 struct reg { struct
pcb.h 35 #include <or1k/reg.h>
42 struct reg reg; member in struct:md_coredump
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_baco.c 44 uint32_t reg; local
50 reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
52 if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
61 uint32_t reg; local
63 reg = RREG32(mmBACO_CNTL);
65 if (reg & BACO_CNTL__BACO_MODE_MASK)
amdgpu_smu9_baco.c 39 uint32_t reg, data; local
49 reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
51 if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
61 uint32_t reg; local
63 reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
65 if (reg & BACO_CNTL__BACO_MODE_MASK)
amdgpu_common_baco.c 32 static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value)
39 data = RREG32(reg);
49 static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask,
58 WREG32(reg, value << shift);
61 data = RREG32(reg);
63 WREG32(reg, data);
66 ret = baco_wait_register(hwmgr, reg, mask, value);
91 u32 i, reg = 0; local
97 reg = entry[i].reg_offset;
98 if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask
111 u32 i, reg = 0; local
    [all...]
  /src/sys/arch/aarch64/include/
asm.h 15 .macro adrl reg, addr
16 adrp \reg, \addr variable
17 add \reg, \reg, #:lo12:\addr variable
pcb.h 37 #include <aarch64/reg.h>
45 struct reg reg; member in struct:md_coredump
  /src/sys/arch/amd64/include/
reg.h 1 /* $NetBSD: reg.h,v 1.11 2022/05/22 11:27:33 andvar Exp $ */
34 * @(#)reg.h 5.5 (Berkeley) 1/18/91
51 struct reg { struct
74 #include <i386/reg.h>
  /src/sys/arch/evbmips/gdium/
gdium_genfb.c 69 pcireg_t reg; local
80 reg = pci_conf_read(&gc->gc_pc, pci_make_tag(&gc->gc_pc, 0, 14, 0),
83 ri->ri_bits = (char *)MIPS_PHYS_TO_KSEG1(BONITO_PCILO_BASE + reg);
  /src/sys/arch/usermode/include/
reg.h 1 /* $NetBSD: reg.h,v 1.4 2018/05/18 20:09:32 reinoud Exp $ */
35 struct reg { struct
  /src/sys/dev/i2c/
au8522mod.h 33 uint16_t reg; member in struct:au8522_modulation_table
  /src/sys/arch/evbarm/stand/board/
becc_mem.c 65 uint32_t start, size, reg, save, heap; local
76 reg = BECC_PCICORE_READ(PCI_CLASS_REG);
78 if (PCI_REVISION(reg) <= BECC_REV_V7)
84 reg = BECC_PCICORE_READ(BECC_SDRAM_BAR);
88 size = PCI_MAPREG_MEM_SIZE(reg);
  /src/sys/arch/hpc/stand/hpcboot/arm/
arm_sa1100_console.h 54 uint8_t reg; local
56 reg = VOLATILE_REF8(_uart_base + 0x20);
57 while ((reg & 0x1) == 0x1 ||(reg & 0x4) == 0);
  /src/sys/arch/i386/pci/
sis85c503.c 129 pcireg_t reg; local
134 reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
136 reg = SIS85C503_CFG_PIRQ_REG(reg, clink);
138 if (reg & SIS85C503_CFG_PIRQ_ROUTE_DISABLE)
141 *irqp = reg & SIS85C503_CFG_PIRQ_INTR_MASK;
151 pcireg_t reg; local
156 reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
159 reg &= ~((SIS85C503_CFG_PIRQ_ROUTE_DISABLE |
161 reg |= (irq << shift)
    [all...]
  /src/sys/arch/macppc/macppc/
interrupts.c 69 uint32_t reg[5]; local
91 if (OF_getprop(macio, "assigned-addresses", reg, sizeof(reg)) != 20)
94 obio_base = reg[2];
97 if (OF_getprop(pic, "reg", reg, 8) < 8)
100 pic_base = obio_base + reg[0];
mainbus.c 71 u_int32_t reg[4]; local
100 ca.ca_reg = reg;
101 ca.ca_nreg = OF_getprop(node, "reg", reg, sizeof(reg));
110 ca.ca_reg = reg;
111 reg[0] = i;
133 ca.ca_nreg = OF_getprop(node, "reg", reg, sizeof(reg));
    [all...]
  /src/sys/arch/mips/ingenic/
ingenic_ehci.c 80 uint32_t reg; local
89 reg = readreg(JZ_USBPCR);
90 reg &= ~(PCR_OTG_DISABLE);
91 writereg(JZ_USBPCR, reg);
94 reg = readreg(JZ_USBPCR1);
95 reg |= PCR_REFCLK_CORE;
96 writereg(JZ_USBPCR1, reg);
99 reg = readreg(JZ_USBPCR1);
100 reg &= ~PCR_CLK_M;
101 reg |= PCR_CLK_48
158 uint32_t reg; local
    [all...]
  /src/sys/arch/x86/pci/
aapic.c 47 pcireg_t reg; local
61 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AMD8131_IOAPIC_CTL);
62 reg |= AMD8131_IOAEN;
63 pci_conf_write(pa->pa_pc, pa->pa_tag, AMD8131_IOAPIC_CTL, reg);
68 reg = pci_conf_read(pa->pa_pc, tag, AMD8131_PCIX_MISC);
69 reg &= ~AMD8131_NIOAMODE;
70 pci_conf_write(pa->pa_pc, tag, AMD8131_PCIX_MISC, reg);
  /src/sys/dev/ofisa/
ess_ofisa.c 80 struct ofisa_reg_desc reg; local
98 n = ofisa_reg_get(aa->oba.oba_phandle, &reg, 1);
103 if (reg.type != OFISA_REG_TYPE_IO) {
107 if (reg.len != ESS_NPORT) {
109 (unsigned long)reg.len, ESS_NPORT);
140 sc->sc_iobase = reg.addr;
141 if (bus_space_map(sc->sc_iot, sc->sc_iobase, reg.len, 0,
sb_ofisa.c 86 struct ofisa_reg_desc reg; local
104 n = ofisa_reg_get(aa->oba.oba_phandle, &reg, 1);
109 if (reg.type != OFISA_REG_TYPE_IO) {
113 if (reg.len != SB_NPORT && reg.len != SBP_NPORT) {
115 (unsigned long)reg.len, SB_NPORT, SBP_NPORT);
134 if (bus_space_map(sc->sc_iot, reg.addr, reg.len, 0, &sc->sc_ioh)) {
140 sc->sc_iobase = reg.addr;
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
mmio_context.h 43 i915_reg_t reg; member in struct:engine_mmio
  /src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_nv50_fence.c 45 struct ttm_mem_reg *reg = &priv->bo->bo.mem; local
46 u32 start = reg->start * PAGE_SIZE;
47 u32 limit = start + reg->size - 1;

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