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Searched defs:reg_sq_cmd (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
kfd_dbgdev.c	496 union SQ_CMD_BITS reg_sq_cmd; local in function:dbgdev_wave_control_set_registers 500 reg_sq_cmd.u32All = 0; 511 reg_sq_cmd.bits.check_vmid = 1; 512 reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD; 513 reg_sq_cmd.bits.wave_id = pMsg->ui32.WaveId; 514 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_SINGLE; 529 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; 536 reg_sq_cmd.bits.check_vmid = 1; 537 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; 551 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_HALT 593 union SQ_CMD_BITS reg_sq_cmd; local in function:dbgdev_wave_control_diq 706 union SQ_CMD_BITS reg_sq_cmd; local in function:dbgdev_wave_control_nodiq 770 union SQ_CMD_BITS reg_sq_cmd; local in function:dbgdev_wave_reset_wavefronts [all...]
kfd_dbgdev.c	496 union SQ_CMD_BITS reg_sq_cmd; local in function:dbgdev_wave_control_set_registers 500 reg_sq_cmd.u32All = 0; 511 reg_sq_cmd.bits.check_vmid = 1; 512 reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD; 513 reg_sq_cmd.bits.wave_id = pMsg->ui32.WaveId; 514 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_SINGLE; 529 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; 536 reg_sq_cmd.bits.check_vmid = 1; 537 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; 551 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_HALT 593 union SQ_CMD_BITS reg_sq_cmd; local in function:dbgdev_wave_control_diq 706 union SQ_CMD_BITS reg_sq_cmd; local in function:dbgdev_wave_control_nodiq 770 union SQ_CMD_BITS reg_sq_cmd; local in function:dbgdev_wave_reset_wavefronts [all...]

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