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/src/sys/arch/riscv/riscv/ | |
cpu_subr.c | 80 volatile u_long riscv_cpu_hatched[N] __cacheline_aligned = { }; variable in typeref:typename:volatile u_long[N]__cacheline_aligned 115 atomic_or_ulong(&riscv_cpu_mbox[n], riscv_cpu_hatched[n]); 147 return (atomic_load_acquire(&riscv_cpu_hatched[off]) & __BIT(bit)) != 0; 160 atomic_or_ulong(&riscv_cpu_hatched[off], bit); |
cpu_subr.c | 80 volatile u_long riscv_cpu_hatched[N] __cacheline_aligned = { }; variable in typeref:typename:volatile u_long[N]__cacheline_aligned 115 atomic_or_ulong(&riscv_cpu_mbox[n], riscv_cpu_hatched[n]); 147 return (atomic_load_acquire(&riscv_cpu_hatched[off]) & __BIT(bit)) != 0; 160 atomic_or_ulong(&riscv_cpu_hatched[off], bit); |