HomeSort by: relevance | last modified time | path
    Searched defs:rq_regs (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer_debug.c 210 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:dcn10_get_rq_states
217 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
218 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
219 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size
    [all...]
dcn10_hubp.h 664 struct _vcs_dpi_display_rq_regs_st rq_regs; member in struct:dcn_hubp_state
708 struct _vcs_dpi_display_rq_regs_st *rq_regs);
amdgpu_dcn10_hw_sequencer_debug.c 210 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:dcn10_get_rq_states
217 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
218 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
219 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size
    [all...]
dcn10_hubp.h 664 struct _vcs_dpi_display_rq_regs_st rq_regs; member in struct:dcn_hubp_state
708 struct _vcs_dpi_display_rq_regs_st *rq_regs);
amdgpu_dcn10_hubp.c 547 struct _vcs_dpi_display_rq_regs_st *rq_regs)
552 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
554 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
555 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
556 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
557 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
559 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
560 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
561 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
562 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size
863 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp1_read_state_common
1036 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp1_read_state
    [all...]
amdgpu_dcn10_hubp.c 547 struct _vcs_dpi_display_rq_regs_st *rq_regs)
552 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
554 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
555 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
556 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
557 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
559 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
560 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
561 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
562 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size
863 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp1_read_state_common
1036 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp1_read_state
    [all...]
amdgpu_dcn10_hw_sequencer.c 201 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:dcn10_log_hubp_states
205 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
206 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
207 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size
    [all...]
amdgpu_dcn10_hw_sequencer.c 201 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:dcn10_log_hubp_states
205 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
206 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
207 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hubp.c 129 struct _vcs_dpi_display_rq_regs_st *rq_regs)
134 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
136 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
137 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
138 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
139 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
141 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
142 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
143 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
144 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size
362 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; local in function:hubp21_validate_dml_output
    [all...]
amdgpu_dcn21_hubp.c 129 struct _vcs_dpi_display_rq_regs_st *rq_regs)
134 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
136 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
137 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
138 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
139 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
141 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
142 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
143 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
144 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size
362 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; local in function:hubp21_validate_dml_output
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hubp.c 199 struct _vcs_dpi_display_rq_regs_st *rq_regs)
204 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
206 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
207 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
208 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
209 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
211 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
212 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
213 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
214 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size
1055 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp2_read_state_common
1228 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp2_read_state
1261 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; local in function:hubp2_validate_dml_output
    [all...]
amdgpu_dcn20_hubp.c 199 struct _vcs_dpi_display_rq_regs_st *rq_regs)
204 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
206 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
207 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
208 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
209 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
211 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
212 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
213 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
214 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size
1055 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp2_read_state_common
1228 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; local in function:hubp2_read_state
1261 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; local in function:hubp2_validate_dml_output
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 452 struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs; local in function:dcn_bw_calc_rq_dlg_ttu
463 memset(rq_regs, 0, sizeof(*rq_regs));
497 dml1_extract_rq_regs(dml, rq_regs, rq_param);
amdgpu_dcn_calcs.c 452 struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs; local in function:dcn_bw_calc_rq_dlg_ttu
463 memset(rq_regs, 0, sizeof(*rq_regs));
497 dml1_extract_rq_regs(dml, rq_regs, rq_param);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 299 struct _vcs_dpi_display_rq_regs_st rq_regs; member in struct:pipe_ctx
core_types.h 299 struct _vcs_dpi_display_rq_regs_st rq_regs; member in struct:pipe_ctx

Completed in 110 milliseconds