| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rv6xx_dpm.c | 165 u32 step_index, struct rv6xx_sclk_stepping *step)
175 r600_engine_clock_entry_enable(rdev, step_index, true);
176 r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false);
179 r600_engine_clock_entry_enable_post_divider(rdev, step_index, false);
184 r600_engine_clock_entry_enable_post_divider(rdev, step_index, true);
185 r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len);
191 r600_engine_clock_entry_set_reference_divider(rdev, step_index,
193 r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider);
194 r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count);
251 u32 step_index = start_index local in function:rv6xx_generate_steps
313 u32 step_index; local in function:rv6xx_invalidate_intermediate_steps_range
[all...] |
| radeon_rv6xx_dpm.c | 165 u32 step_index, struct rv6xx_sclk_stepping *step)
175 r600_engine_clock_entry_enable(rdev, step_index, true);
176 r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false);
179 r600_engine_clock_entry_enable_post_divider(rdev, step_index, false);
184 r600_engine_clock_entry_enable_post_divider(rdev, step_index, true);
185 r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len);
191 r600_engine_clock_entry_set_reference_divider(rdev, step_index,
193 r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider);
194 r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count);
251 u32 step_index = start_index local in function:rv6xx_generate_steps
313 u32 step_index; local in function:rv6xx_invalidate_intermediate_steps_range
[all...] |
