| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 979 int vlevel,
988 ASSERT(vlevel < dml->soc.num_states);
990 pipes[0].clks_cfg.voltage = vlevel;
991 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
992 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1052 int vlevel, vlevel_max; local in function:dcn21_calculate_wm
1105 vlevel = 0;
1107 vlevel = vlevel_max;
1108 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1112 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max)
1136 int vlevel = 0; local in function:dcn21_validate_bandwidth
[all...] |
| amdgpu_dcn21_resource.c | 979 int vlevel,
988 ASSERT(vlevel < dml->soc.num_states);
990 pipes[0].clks_cfg.voltage = vlevel;
991 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
992 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1052 int vlevel, vlevel_max; local in function:dcn21_calculate_wm
1105 vlevel = 0;
1107 vlevel = vlevel_max;
1108 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1112 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max)
1136 int vlevel = 0; local in function:dcn21_validate_bandwidth
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 2458 int vlevel,
2502 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2503 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
2506 if (vlevel > context->bw_ctx.dml.soc.num_states)
2507 vlevel = vlevel_split;
2520 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1)
2533 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = dm_odm_combine_mode_2to1;
2536 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx]
2556 int pipe_cnt, i, pipe_idx, vlevel; local in function:dcn20_fast_validate_bw
2886 int vlevel = 0; local in function:dcn20_validate_bandwidth_internal
[all...] |
| amdgpu_dcn20_resource.c | 2458 int vlevel,
2502 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2503 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
2506 if (vlevel > context->bw_ctx.dml.soc.num_states)
2507 vlevel = vlevel_split;
2520 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1)
2533 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = dm_odm_combine_mode_2to1;
2536 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx]
2556 int pipe_cnt, i, pipe_idx, vlevel; local in function:dcn20_fast_validate_bw
2886 int vlevel = 0; local in function:dcn20_validate_bandwidth_internal
[all...] |
