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    Searched defs:wb_gpu_addr (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 2982 uint64_t hqd_gpu_addr, wb_gpu_addr; local in function:gfx_v10_0_gfx_mqd_init
3023 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3024 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3026 upper_32_bits(wb_gpu_addr) & 0xffff;
3029 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3030 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3031 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3226 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; local in function:gfx_v10_0_compute_mqd_init
3304 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3305 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc
    [all...]
amdgpu_gfx_v7_0.c 2942 u64 wb_gpu_addr; local in function:gfx_v7_0_mqd_init
2997 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2998 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2999 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3002 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3003 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3005 upper_32_bits(wb_gpu_addr) & 0xffff;
amdgpu_gfx_v10_0.c 2982 uint64_t hqd_gpu_addr, wb_gpu_addr; local in function:gfx_v10_0_gfx_mqd_init
3023 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3024 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3026 upper_32_bits(wb_gpu_addr) & 0xffff;
3029 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3030 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3031 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3226 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; local in function:gfx_v10_0_compute_mqd_init
3304 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3305 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc
    [all...]
amdgpu_gfx_v7_0.c 2942 u64 wb_gpu_addr; local in function:gfx_v7_0_mqd_init
2997 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2998 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2999 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3002 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3003 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3005 upper_32_bits(wb_gpu_addr) & 0xffff;
amdgpu_gfx_v10_0.c 2982 uint64_t hqd_gpu_addr, wb_gpu_addr; local in function:gfx_v10_0_gfx_mqd_init
3023 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3024 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3026 upper_32_bits(wb_gpu_addr) & 0xffff;
3029 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3030 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3031 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3226 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; local in function:gfx_v10_0_compute_mqd_init
3304 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3305 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc
    [all...]
amdgpu_gfx_v7_0.c 2942 u64 wb_gpu_addr; local in function:gfx_v7_0_mqd_init
2997 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2998 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2999 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3002 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3003 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3005 upper_32_bits(wb_gpu_addr) & 0xffff;
amdgpu_gfx_v8_0.c 4436 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; local in function:gfx_v8_0_mqd_init
4499 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4500 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4502 upper_32_bits(wb_gpu_addr) & 0xffff;
4505 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4506 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4507 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
amdgpu_gfx_v8_0.c 4436 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; local in function:gfx_v8_0_mqd_init
4499 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4500 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4502 upper_32_bits(wb_gpu_addr) & 0xffff;
4505 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4506 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4507 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
amdgpu_gfx_v8_0.c 4436 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; local in function:gfx_v8_0_mqd_init
4499 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4500 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4502 upper_32_bits(wb_gpu_addr) & 0xffff;
4505 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4506 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4507 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
amdgpu_gfx_v9_0.c 3323 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; local in function:gfx_v9_0_mqd_init
3412 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3413 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3415 upper_32_bits(wb_gpu_addr) & 0xffff;
3418 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3419 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3420 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
amdgpu_gfx_v9_0.c 3323 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; local in function:gfx_v9_0_mqd_init
3412 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3413 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3415 upper_32_bits(wb_gpu_addr) & 0xffff;
3418 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3419 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3420 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
amdgpu_gfx_v9_0.c 3323 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; local in function:gfx_v9_0_mqd_init
3412 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3413 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3415 upper_32_bits(wb_gpu_addr) & 0xffff;
3418 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3419 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3420 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cik.c 4543 u64 wb_gpu_addr; local in function:cik_cp_compute_resume
4704 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;
4706 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;
4707 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4708 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4715 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;
4717 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;
4718 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
4720 upper_32_bits(wb_gpu_addr) & 0xffff;
radeon_cik.c 4543 u64 wb_gpu_addr; local in function:cik_cp_compute_resume
4704 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;
4706 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;
4707 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4708 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4715 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;
4717 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;
4718 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
4720 upper_32_bits(wb_gpu_addr) & 0xffff;
radeon_cik.c 4543 u64 wb_gpu_addr; local in function:cik_cp_compute_resume
4704 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;
4706 wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;
4707 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4708 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4715 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;
4717 wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;
4718 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
4720 upper_32_bits(wb_gpu_addr) & 0xffff;

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