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    Searched defs:write_val (Results 1 - 25 of 26) sorted by relevancy

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  /src/sys/arch/arm/rockchip/
rk_cru_gate.c 48 const uint32_t write_val = enable ? 0 : gate->mask; local
50 CRU_WRITE(sc, gate->reg, write_mask | write_val);
rk_cru_gate.c 48 const uint32_t write_val = enable ? 0 : gate->mask; local
50 CRU_WRITE(sc, gate->reg, write_mask | write_val);
rk_cru_mux.c 78 const uint32_t write_val = __SHIFTIN(index, mux->mask); local
82 syscon_write_4(sc->sc_grf, mux->reg, write_mask | write_val);
85 CRU_WRITE(sc, mux->reg, write_mask | write_val);
rk_cru_mux.c 78 const uint32_t write_val = __SHIFTIN(index, mux->mask); local
82 syscon_write_4(sc->sc_grf, mux->reg, write_mask | write_val);
85 CRU_WRITE(sc, mux->reg, write_mask | write_val);
rk3288_usb.c 125 uint32_t write_mask, write_val; local
128 write_val = enable ? 0 : GRF_UOCn_CON0_SIDDQ;
131 syscon_write_4(sc->sc_syscon, sc->sc_reg, write_mask | write_val);
rk_cru_arm.c 107 const uint32_t write_val = __SHIFTIN(arm_rate->div - 1, local
109 CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
124 uint32_t write_mask, write_val; local
163 write_val = cpu_rate->divs[i].val;
164 CRU_WRITE(sc, cpu_rate->divs[i].reg, write_mask | write_val);
172 write_val = __SHIFTIN(0, arm->divs[i].mask);
173 CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
223 const uint32_t write_val = __SHIFTIN(mux, arm->mux_mask); local
225 CRU_WRITE(sc, arm->mux_reg, write_mask | write_val);
rk_cru_composite.c 53 const uint32_t write_val = enable ? 0 : composite->gate_mask; local
55 CRU_WRITE(sc, composite->gate_reg, write_mask | write_val);
205 uint32_t write_val = __SHIFTIN(best_div - 1, composite->div_mask); local
208 write_val |= __SHIFTIN(best_mux, composite->mux_mask);
211 CRU_WRITE(sc, composite->muxdiv_reg, write_mask | write_val);
250 const uint32_t write_val = __SHIFTIN(mux, composite->mux_mask); local
252 CRU_WRITE(sc, composite->muxdiv_reg, write_mask | write_val);
rk3288_usb.c 125 uint32_t write_mask, write_val; local
128 write_val = enable ? 0 : GRF_UOCn_CON0_SIDDQ;
131 syscon_write_4(sc->sc_syscon, sc->sc_reg, write_mask | write_val);
rk_cru_arm.c 107 const uint32_t write_val = __SHIFTIN(arm_rate->div - 1, local
109 CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
124 uint32_t write_mask, write_val; local
163 write_val = cpu_rate->divs[i].val;
164 CRU_WRITE(sc, cpu_rate->divs[i].reg, write_mask | write_val);
172 write_val = __SHIFTIN(0, arm->divs[i].mask);
173 CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
223 const uint32_t write_val = __SHIFTIN(mux, arm->mux_mask); local
225 CRU_WRITE(sc, arm->mux_reg, write_mask | write_val);
rk_cru_composite.c 53 const uint32_t write_val = enable ? 0 : composite->gate_mask; local
55 CRU_WRITE(sc, composite->gate_reg, write_mask | write_val);
205 uint32_t write_val = __SHIFTIN(best_div - 1, composite->div_mask); local
208 write_val |= __SHIFTIN(best_mux, composite->mux_mask);
211 CRU_WRITE(sc, composite->muxdiv_reg, write_mask | write_val);
250 const uint32_t write_val = __SHIFTIN(mux, composite->mux_mask); local
252 CRU_WRITE(sc, composite->muxdiv_reg, write_mask | write_val);
rk3399_pmucru.c 248 const uint32_t write_val = pll->mode_mask; local
249 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
rk_anxdp.c 81 const uint32_t write_val = crtc_index == 0 ? EDP_LCDC_SEL : 0; local
84 syscon_write_4(sc->sc_grf, RK3399_GRF_SOC_CON20, write_mask | write_val);
rk_dwhdmi.c 102 const uint32_t write_val = crtc_index == 0 ? HDMI_LCDC_SEL : 0; local
105 syscon_write_4(sc->sc_grf, RK3399_GRF_SOC_CON20, write_mask | write_val);
rk_usb.c 121 uint32_t reg, write_mask, write_val; local
127 write_val = 0;
134 write_val = 0;
141 syscon_write_4(sc->sc_syscon, reg, write_mask | write_val);
151 uint32_t reg, write_mask, write_val; local
157 write_val = RK3328_USBPHY_COMMONONN;
164 write_val = RK3399_USBPHY_COMMONONN;
171 syscon_write_4(sc->sc_syscon, reg, write_mask | write_val);
303 uint32_t reg, write_mask, write_val; local
310 write_val = enable ? 0 : 0x1d1
342 uint32_t reg, write_mask, write_val; local
    [all...]
rk3399_pmucru.c 248 const uint32_t write_val = pll->mode_mask; local
249 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
rk_anxdp.c 81 const uint32_t write_val = crtc_index == 0 ? EDP_LCDC_SEL : 0; local
84 syscon_write_4(sc->sc_grf, RK3399_GRF_SOC_CON20, write_mask | write_val);
rk_dwhdmi.c 102 const uint32_t write_val = crtc_index == 0 ? HDMI_LCDC_SEL : 0; local
105 syscon_write_4(sc->sc_grf, RK3399_GRF_SOC_CON20, write_mask | write_val);
rk_usb.c 121 uint32_t reg, write_mask, write_val; local
127 write_val = 0;
134 write_val = 0;
141 syscon_write_4(sc->sc_syscon, reg, write_mask | write_val);
151 uint32_t reg, write_mask, write_val; local
157 write_val = RK3328_USBPHY_COMMONONN;
164 write_val = RK3399_USBPHY_COMMONONN;
171 syscon_write_4(sc->sc_syscon, reg, write_mask | write_val);
303 uint32_t reg, write_mask, write_val; local
310 write_val = enable ? 0 : 0x1d1
342 uint32_t reg, write_mask, write_val; local
    [all...]
rk_cru_pll.c 253 const uint32_t write_val = pll->mode_mask; local
254 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
rk_cru_pll.c 253 const uint32_t write_val = pll->mode_mask; local
254 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
rk3399_cru.c 1124 uint32_t write_mask, write_val; local
1138 write_val = 0;
1139 CRU_WRITE(sc, CLKSEL_CON(49), write_mask | write_val);
1140 CRU_WRITE(sc, CLKSEL_CON(50), write_mask | write_val);
rk3399_iomux.c 336 const uint32_t write_val = drv_val & 0xffff; local
342 WR4(syscon, reg, write_val | write_mask);
rk_gmac.c 106 uint32_t write_mask, write_val; local
112 write_val = __SHIFTIN(RK3288_GRF_SOC_CON1_GMAC_PHY_INTF_SEL_RGMII,
115 write_mask | write_val);
122 write_val = 0;
134 write_mask | write_val);
144 uint32_t write_mask, write_val; local
151 write_val = RK3288_GRF_SOC_CON1_GMAC_CLK_SEL_2_5M;
154 write_val = RK3288_GRF_SOC_CON1_GMAC_CLK_SEL_25M;
158 write_val = RK3288_GRF_SOC_CON1_GMAC_CLK_SEL_125M;
162 write_mask | write_val);
190 uint32_t write_mask, write_val; local
275 uint32_t write_mask, write_val; local
    [all...]
rk3399_cru.c 1124 uint32_t write_mask, write_val; local
1138 write_val = 0;
1139 CRU_WRITE(sc, CLKSEL_CON(49), write_mask | write_val);
1140 CRU_WRITE(sc, CLKSEL_CON(50), write_mask | write_val);
rk3399_iomux.c 336 const uint32_t write_val = drv_val & 0xffff; local
342 WR4(syscon, reg, write_val | write_mask);

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