Searched refs:AGILEX5_L4_MAIN_CLK (Results 1 - 2 of 2) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dintel,agilex5-clkmgr.h57 #define AGILEX5_L4_MAIN_CLK 39 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi269 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
286 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
316 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
333 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;

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