Searched refs:CLK_TOP_APLL1_DIV0 (Results 1 - 3 of 3) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmt8173-clk.h133 #define CLK_TOP_APLL1_DIV0 121 macro
H A Dmediatek,mt6795-clk.h128 #define CLK_TOP_APLL1_DIV0 115 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi869 <&topckgen CLK_TOP_APLL1_DIV0>,

Completed in 5 milliseconds