Searched refs:RGMII (Results 1 - 25 of 32) sorted by relevance
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| /src/sys/external/gpl2/dts/dist/include/dt-bindings/phy/ |
| H A D | phy-lan966x-serdes.h | 12 #define RGMII(x) (SERDES6G_MAX + 1 + (x)) macro
13 #define RGMII_MAX RGMII(2)
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| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-lx2160a-bluebox3-rev-a.dts | 15 /* The RGMII PHYs have a different MDIO address */
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| H A D | fsl-ls1028a-kontron-sl28-var4.dts | 6 * extends the base and provides one more port connected via RGMII.
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| H A D | fsl-ls1028a-kontron-sl28-var1.dts | 7 * port is connected via RGMII. This port is not TSN aware.
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| H A D | fsl-ls1028a-qds.dts | 99 /* on-board RGMII PHY */
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| H A D | imx8mp-dhcom-som.dtsi | 820 pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */
871 pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */
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| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-gxm-vega-s96.dts | 28 /* External PHY is in RGMII */
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| H A D | meson-gxl-s905d-p230.dts | 71 /* External PHY is in RGMII */
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| H A D | meson-gxm-q200.dts | 53 /* External PHY is in RGMII */
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| H A D | meson-gxm-nexbox-a1.dts | 167 /* External PHY is in RGMII */
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| H A D | meson-gxbb-nanopi-k2.dts | 251 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
253 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
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| H A D | meson-gxbb-odroidc2.dts | 294 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
296 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
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| H A D | meson-gxm-rbox-pro.dts | 169 /* External PHY is in RGMII */
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| H A D | meson-gxm-khadas-vim2.dts | 227 /* External PHY is in RGMII */
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| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/ |
| H A D | jh7100-starfive-visionfive-v1.dts | 26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/microchip/ |
| H A D | at91-sama5d3_eds.dts | 211 /* Reserved for reset signal to the RGMII connector. */
217 /* Reserved for an interrupt line from the RMII and RGMII connectors. */
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6qdl-wandboard-revd1.dtsi | 147 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */
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| H A D | imx6qp-prtwd3.dts | 460 /* Configure clock provider for RGMII ref clock */
462 /* Configure clock consumer for RGMII ref clock */
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| H A D | imx6qdl-sr-som.dtsi | 133 * As the RMII pins are also connected to RGMII
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| H A D | imx6dl-qmx6.dtsi | 441 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/ls/ |
| H A D | ls1021a-tsn.dts | 121 /* RGMII delays added via PCB traces */
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/st/ |
| H A D | stm32mp151c-mect1s.dts | 246 /* RGMII mode is not working properly, using RMII instead. */
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| H A D | stm32mp15xc-lxa-tac.dtsi | 249 /* Reduce EMI emission by reducing RGMII drive strength */
469 /* Reduce RGMII EMI emissions by reducing drive strength */
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/marvell/ |
| H A D | armada-385-clearfog-gtr.dtsi | 27 6..17 - RGMII
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| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| H A D | stingray.dtsi | 325 mdio@10 { /* RGMII */
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