| /src/sys/arch/m68k/include/ |
| reg.h | 48 int r_regs[16]; /* D0-D7/A0-A7 */
83 #define A7 (15)
86 #define SP A7
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| vexpress-v2p-ca15_a7.dts | 60 compatible = "arm,cortex-a7";
70 compatible = "arm,cortex-a7";
80 compatible = "arm,cortex-a7";
234 pmu-a7 {
235 compatible = "arm,cortex-a7-pmu";
275 /* A7 PLL 0 reference clock */
284 /* A7 PLL 1 reference clock */
348 volt-a7 {
349 /* A7 CPU core voltage */
352 regulator-name = "A7 Vcore"
[all...] |
| exynos5422-cpus.dtsi | 8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
16 * from the LITTLE: Cortex-A7.
58 compatible = "arm,cortex-a7";
71 compatible = "arm,cortex-a7";
84 compatible = "arm,cortex-a7";
97 compatible = "arm,cortex-a7";
|
| exynos5422-odroidxu3-lite.dts | 39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
|
| exynos5422-odroidxu3.dts | 48 /* A7 cluster: VDD_KFC */
|
| exynos5420-cpus.dtsi | 17 * from the LITTLE: Cortex-A7.
107 compatible = "arm,cortex-a7";
119 compatible = "arm,cortex-a7";
131 compatible = "arm,cortex-a7";
143 compatible = "arm,cortex-a7";
|
| kirkwood-openblocks_a7.dts | 3 * Device Tree file for OpenBlocks A7 board
18 compatible = "plathome,openblocks-a7", "marvell,kirkwood-88f6283", "marvell,kirkwood";
|
| aspeed-bmc-opp-zaius.dts | 472 pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
482 /*A0-A7*/ "","cfam-reset","","","","","","",
|
| aspeed-bmc-amd-ethanolx.dts | 103 /*A0-A7*/ "","","FAULT_LED","CHASSIS_ID_LED","","","","",
|
| aspeed-bmc-opp-nicole.dts | 219 /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","",
|
| aspeed-bmc-opp-romulus.dts | 235 /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","",
|
| aspeed-bmc-facebook-tiogapass.dts | 123 /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","",
|
| aspeed-bmc-inspur-nf5280m6.dts | 142 /*A0-A7*/ "","MAC2LINK","BMC_RESET_CPLD","","BMC_SCL9","","MAC2MDC_R","",
|
| aspeed-bmc-opp-witherspoon.dts | 202 /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","",
|
| exynos5800-peach-pi.dts | 160 * Peach Pi board uses SoC revision with lower maximum frequency for A7 cores
162 * update A7 OPPs table accordingly.
|
| aspeed-bmc-ampere-mtjade.dts | 569 /*A0-A7*/ "","","","S0_BMC_SPECIAL_BOOT","","","","",
|
| aspeed-bmc-inspur-fp5280g2.dts | 209 /*A0-A7*/ "","","","","","","","",
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/pic32/ |
| pic32mzda_sk.dts | 102 pins = "A6", "D4", "G13", "G12", "G14", "A7", "A0";
|
| /src/lib/libm/ld128/ |
| k_expl.h | 76 A7 = 1.9841269841269470e-4, /* 0x1.a01a01a019f91p-13 */
257 dr * (A7 + dr * (A8 + dr * (A9 + dr * A10))))))));
|
| s_expl.c | 286 dr * (A7 + dr * (A8 + dr * (A9 + dr * A10))))))));
|
| /src/sys/arch/m68k/fpsp/ |
| fpsp.h | 45 * fsave -(a7)
52 * A7 ---> +-------------------------------+
72 * The fsave frame is also accessible 'from the top' via A7.
79 * frestore (a7)+
|
| l_fpsp.h | 63 * A7 ---> +-------------------------------+
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/ |
| k3-j7200-som-p0.dtsi | 100 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
| /src/libexec/ld.aout_so/ |
| ld.so.i386.uue | 160 MW(M-T`,YBTT,B7D(B5$,.U4(#X2K_O__B57HQT7P`0```(-]U``/A7?_____
290 M@[U\____`'0=BTV,4>C3]___QT6,`````,>%?/___P````"#Q`2+A7#___]0
324 M____Z9P.``"-=@")=8"-1;2)A7#___^)A4C___^)1?3'1?P`````QT7X````
327 M_W1<BY5X____BX5P____B1")>`0!??R#P`B)A7#___^+3?B-00&)1?B)P8/Y
380 M____4(M5"%+H5O3__XG!@\0(A<D/A9D$``"+A4C___^)A7#___^-DUAD__^)
390 M@\;P@_X0?Y&+E3C___^+A7#___^)$(EP!`%U_(/`"(F%</___XM-^(U!`8E%
395 M_XF5./___X/&\(/^$'^1BY4X____BX5P____B1")<`0!=?R#P`B)A7#___^+
397 ME4C___^)E7#___^+E7C___^+A7#___^)$(EX!`%]_(/`"(F%</___XM-^(U!
405 M4(M5"%+H].___XG!@\0(A<EU.\=%^`````"+A4C___^)A7#____IX_'__XUV
813 M,3DY."\Q,2\Q-2`Q-SHQ-CHR-R!C:')I<W1O<R!%>'`@)`"-=@!5B>6#[`A7
[all...] |
| /src/tests/bin/sh/ |
| t_patterns.sh | 625 for W in AA A7 8x 77; do
|
