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    Searched refs:AR9344_CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/mips/atheros/include/
ar9344reg.h	124 #define AR9344_CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV __BITS(10,14)
/src/sys/arch/mips/atheros/
ar9344.c	181 AR9344_CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV);

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