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    Searched refs:AR_BEACON (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/isc/atheros_hal/dist/ar5210/
ar5210_beacon.c 43 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
93 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
145 OS_REG_WRITE(ah, AR_BEACON,
146 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
ar5210_reset.c 272 * Writing to AR_BEACON will start timers. Hence it should be
277 OS_REG_WRITE(ah, AR_BEACON,
278 (OS_REG_READ(ah, AR_BEACON) &
466 regBeacon = OS_REG_READ(ah, AR_BEACON);
467 OS_REG_WRITE(ah, AR_BEACON, regBeacon & ~AR_BEACON_EN);
563 OS_REG_WRITE(ah, AR_BEACON, regBeacon);
ar5210_misc.c 370 uint32_t val = OS_REG_READ(ah, AR_BEACON);
372 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
ar5210reg.h 77 #define AR_BEACON 0x8024 /* Beacon control */
  /src/sys/external/isc/atheros_hal/dist/ar5211/
ar5211_beacon.c 46 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
104 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
152 OS_REG_WRITE(ah, AR_BEACON,
153 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
ar5211_misc.c 367 uint32_t val = OS_REG_READ(ah, AR_BEACON);
369 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
ar5211_reset.c 529 * Writing to AR_BEACON will start timers. Hence it should
534 OS_REG_WRITE(ah, AR_BEACON,
535 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
ar5211reg.h 246 #define AR_BEACON 0x8020 /* beacon control value/mode bits */
  /src/sys/external/isc/atheros_hal/dist/ar5212/
ar5212_beacon.c 54 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF);
56 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
115 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
162 OS_REG_WRITE(ah, AR_BEACON,
163 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
ar5212_misc.c 276 uint32_t val = OS_REG_READ(ah, AR_BEACON);
278 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
286 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
ar5212_reset.c 68 ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \
179 * bit in the AR_BEACON register; it also has the quirk
583 * Writing to AR_BEACON will start timers. Hence it should
588 OS_REG_WRITE(ah, AR_BEACON,
589 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
ar5212reg.h 259 #define AR_BEACON 0x8020 /* MAC beacon control value/mode bits */
  /src/sys/external/isc/atheros_hal/dist/ar5312/
ar5312_reset.c 54 ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \
148 * bit in the AR_BEACON register; it also has the quirk
546 * Writing to AR_BEACON will start timers. Hence it should
551 OS_REG_WRITE(ah, AR_BEACON,
552 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));

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