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    Searched refs:AR_PHY_PLL_CTL_44 (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/isc/atheros_hal/dist/ar5211/
ar5211phy.h 45 #define AR_PHY_PLL_CTL_44 0x19 /* 44 MHz for 11b channels and FPGA */
ar5211_attach.c 248 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
ar5211_reset.c 614 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44);
  /src/sys/external/isc/atheros_hal/dist/ar5212/
ar5212phy.h 142 #define AR_PHY_PLL_CTL_44 0xab /* 44 MHz for 11b, 11g */
ar5212_reset.c 910 phyPLL = AR_PHY_PLL_CTL_44;
  /src/sys/external/isc/atheros_hal/dist/ar5312/
ar5312_reset.c 710 phyPLL = AR_PHY_PLL_CTL_44;

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