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    Searched refs:AUX_DPHY_RX_CONTROL0 (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_link_encoder.h 43 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
111 uint32_t AUX_DPHY_RX_CONTROL0;
amdgpu_dce_link_encoder.c 509 addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
514 AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_link_encoder.h 39 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
76 uint32_t AUX_DPHY_RX_CONTROL0;
amdgpu_dcn10_link_encoder.c 1403 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_link_encoder.c 292 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
303 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);

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