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    Searched refs:AlignedAddr (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
Allocator.h 181 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment);
182 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize);
183 char *AlignedPtr = (char*)AlignedAddr;
191 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment);
192 assert(AlignedAddr + SizeToAllocate <= (uintptr_t)End &&
194 char *AlignedPtr = (char*)AlignedAddr;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
AtomicExpandPass.cpp 585 Value *AlignedAddr = nullptr;
607 O << " AlignedAddr: ";
608 PrintObj(PMV.AlignedAddr);
628 /// AlignedAddr: Addr rounded down to a multiple of WordSize
653 PMV.AlignedAddr = Addr;
665 PMV.AlignedAddr = Builder.CreateIntToPtr(
667 "AlignedAddr");
790 OldResult = insertRMWCmpXchgLoop(Builder, PMV.WordType, PMV.AlignedAddr,
796 OldResult = insertRMWLLSCLoop(Builder, PMV.WordType, PMV.AlignedAddr,
832 Builder.CreateAtomicRMW(Op, PMV.AlignedAddr, NewOperand
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  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.h 442 Value *AlignedAddr, Value *Incr,
449 Value *AlignedAddr, Value *CmpVal,
RISCVISelLowering.cpp 8351 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
8356 Type *Tys[] = {AlignedAddr->getType()};
8382 {AlignedAddr, Incr, Mask, SextShamt, Ordering});
8385 Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
8403 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
8414 Type *Tys[] = {AlignedAddr->getType()};
8418 MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 1660 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1768 // and alignedaddr,ptr,masklsb2
1779 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1806 .addReg(AlignedAddr)
1909 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1952 // and alignedaddr,ptr,masklsb2
1966 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1998 .addReg(AlignedAddr)
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 1882 Value *AlignedAddr, Value *Incr,
1892 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 3921 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3950 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
4037 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
4053 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,

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