| radeon_sumo_dpm.c | 539 u32 cg_sclk_dpm_ctrl_3; local in function:sumo_set_allos_gnb_slow
544 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
545 cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
546 cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
548 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
606 if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
614 WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
619 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE)
947 u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3); local in function:sumo_program_ttt
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