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    Searched refs:CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_sh_mask.h 2882 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00ff0000L
gfx_7_2_sh_mask.h 3139 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
gfx_8_0_sh_mask.h 3753 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
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gfx_8_1_sh_mask.h 4275 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
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  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_sh_mask.h 1239 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
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gc_9_1_sh_mask.h 1138 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
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gc_9_2_1_sh_mask.h 1105 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
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gc_10_1_0_sh_mask.h 6718 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x000FFC00L
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