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Searched refs:DPG_PIPE_LOW_POWER_CONTROL (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_mem_input.h	`80 SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\ 113 uint32_t DPG_PIPE_LOW_POWER_CONTROL; 225 SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\ 226 SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ 227 SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ 228 SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh)`
amdgpu_dce_mem_input.c	`219 if (REG(DPG_PIPE_LOW_POWER_CONTROL)) { 223 REG_UPDATE_3(DPG_PIPE_LOW_POWER_CONTROL, 228 REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL,`

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