HomeSort by: relevance | last modified time | path
    Searched refs:DP_SINK_COUNT_ESI (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_dp_mst.c 720 DP_SINK_COUNT_ESI, esi, 8);
730 DP_SINK_COUNT_ESI + 1, &esi[1], 3);
736 DP_SINK_COUNT_ESI, esi, 8);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_dp.c 1767 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1771 DP_SINK_COUNT_ESI,
1778 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1779 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1780 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1781 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1782 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1783 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm_mst_types.c 57 #define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
amdgpu_dm.c 1966 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1982 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1984 dpcd_addr = DP_SINK_COUNT_ESI;
  /src/sys/external/bsd/drm2/dist/include/drm/
drm_dp_helper.h 858 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
  /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/
nouveau_dispnv50_disp.c 1343 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1353 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dp.c 4583 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
5062 DP_SINK_COUNT_ESI+1,

Completed in 28 milliseconds