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    Searched refs:Demanded (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
BDCE.cpp 52 // If all bits of a user are demanded, then we know that nothing below that
62 // demanded bits. Normally, the only way to reach an instruction with an
66 // demanded bits of the function call's return value. A void-returning
83 // If all bits of a user are demanded, then we know that nothing below
104 // during analysis or have no demanded bits.
118 APInt Demanded = DB.getDemandedBits(SE);
122 if (Demanded.countLeadingZeros() >= (DestBitSize - SrcBitSize)) {
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineSimplifyDemanded.cpp 29 /// constant that are not demanded. If so, shrink the constant and return true.
31 const APInt &Demanded) {
41 // If there are no bits set that aren't demanded, nothing to do.
42 if (C->isSubsetOf(Demanded))
45 // This instruction is producing bits that are not demanded. Shrink the RHS.
46 I->setOperand(OpNo, ConstantInt::get(Op->getType(), *C & Demanded));
86 /// demanded bits. When this function is called, it is known that only the bits
105 /// operands based on the information about what bits are demanded. This returns
107 /// in the context where the specified bits are demanded, but not for all users.
144 // only reflects the bits demanded by *one* of the users
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 2800 APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24);
2805 SDValue DemandedLHS = TLI.SimplifyMultipleUseDemandedBits(LHS, Demanded, DAG);
2806 SDValue DemandedRHS = TLI.SimplifyMultipleUseDemandedBits(RHS, Demanded, DAG);
2814 if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI))
2816 if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI))
4064 APInt Demanded = APInt::getBitsSet(32,
4072 if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) ||
4073 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) {
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 3294 /// constant that are not demanded. If so, shrink the constant and return
3317 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
3326 /// be accurate for those bits in the Demanded masks.
3451 /// Attempt to simplify any target nodes based on the demanded vector
3460 /// Attempt to simplify any target nodes based on the demanded bits/elts,
3464 /// be accurate for those bits in the Demanded masks.
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 501 /// bits set in that constant that are not demanded, then clear those bits and
558 const APInt &Demanded,
580 unsigned DemandedSize = Demanded.getActiveBits();
593 assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?");
722 // If all of the demanded bits are known 1 on one side, return the other.
735 // If all of the demanded bits are known zero on one side, return the
748 // If all of the demanded bits are known zero on one side, return the
793 // If none of the extended bits are demanded, eliminate the sextinreg.
843 // If all the demanded elts are from one operand and are inline,
986 // Collect the known bits that are shared by every demanded element
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 1550 const APInt &Demanded,
1563 uint64_t DemandedBits = Demanded.getZExtValue();
1565 // Clear bits that are not demanded.
1569 // The goal here is to set the non-demanded bits in a way that minimizes
1571 // we set the non-demanded bits to the value of the preceding demanded bits.
1573 // non-demanded bit), we copy bit0 (1) to the least significant 'x',
1600 // Return if there is mismatch in any of the demanded bits of Imm and Hi.
1618 assert(((OldImm ^ NewImm) & Demanded.getZExtValue()) == 0 &&
1619 "demanded bits should never be altered")
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 13310 // FIXME: Use demanded bits?
13333 // FIXME: Use demanded bits?
13346 // FIXME: Handle other patterns of known/demanded bits.
13881 // the bits being cleared by the AND are not demanded by the BFI.
15804 // Qd (Op0) are demanded from a VMOVN, depending on whether we are inserting
16373 // demanded (though a truncating store, for example).
16414 // demanded (though a truncating store, for example).
16896 // Capture demanded bits information that would be otherwise lost.
18228 unsigned Demanded = DemandedBits.getZExtValue();
18229 unsigned ShrunkMask = Mask & Demanded;
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