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    Searched refs:DimIdx (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 3423 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
3430 if (DimIdx == -1)
3433 unsigned Dim = Inst.getOperand(DimIdx).getImm();
3507 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
3508 assert(DimIdx != -1);
3510 unsigned Dim = Inst.getOperand(DimIdx).getImm();
3637 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
3638 if (DimIdx < 0)
3641 long Imm = Inst.getOperand(DimIdx).getImm();
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 716 unsigned DimIdx =
723 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 4065 int DimIdx, int NumVAddrs) {
4070 MachineOperand &SrcOp = MI.getOperand(DimIdx + I);
4089 MI.getOperand(DimIdx).setReg(VAddr.getReg(0));
4093 MachineOperand &SrcOp = MI.getOperand(DimIdx + I);
4095 MI.getOperand(DimIdx + I).setReg(AMDGPU::NoRegister);
SIISelLowering.cpp 5932 unsigned DimIdx, unsigned EndIdx,
5935 for (unsigned I = DimIdx; I < EndIdx; I++) {
5944 ((NumGradients / 2) % 2 == 1 && (I == DimIdx + (NumGradients / 2) - 1 ||
5945 I == DimIdx + NumGradients - 1))) {

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