| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 319 // Expand to fneg + fadd.
484 setOperationAction(ISD::FNEG, VT, Expand);
561 setTargetDAGCombine(ISD::FNEG);
1715 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
2097 // (frem x, y) -> (fma (fneg (ftrunc (fdiv x, y))), y, x)
2107 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags);
2480 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
3491 // select c, (fneg x), (fneg y) -> fneg (select c, x, y
[all...] |
| AMDGPUISelDAGToDAG.cpp | 2668 if (Src.getOpcode() == ISD::FNEG) {
2710 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
2753 if (Src.getOpcode() == ISD::FNEG) {
2764 if (Lo.getOpcode() == ISD::FNEG) {
2769 if (Hi.getOpcode() == ISD::FNEG) {
2872 // Be careful about folding modifiers if we already have an abs. fneg is
2873 // applied last, so we don't want to apply an earlier fneg.
|
| SIISelLowering.cpp | 647 setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
649 // allows matching fneg (fabs x) patterns)
732 setOperationAction(ISD::FNEG, MVT::v2f32, Legal);
742 setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
755 setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
4312 // free fneg'd operands. As long as we have fast FMA (controlled by
4521 case ISD::FNEG:
4872 case ISD::FNEG: {
8261 // -1.0 / x -> rcp (fneg x)
8262 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS)
[all...] |
| AMDGPUTargetTransformInfo.cpp | 703 case ISD::FNEG:
704 // Use the backend' estimation. If fneg is not free each element will cost
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 856 FNEG,
|
| /src/sys/arch/m68k/m68k/ |
| db_disasm.h | 365 #define FNEG ENCFT(0,1,1,0,1,0)
|
| db_disasm.c | 1453 case FNEG:
1454 get_fpustdGEN(dbuf,ext,"fneg");
|
| /src/sys/arch/sparc/include/ |
| instr.h | 407 #define FNEG 0x04
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 1697 case ISD::FNEG: return visitFNEG(N);
12400 FPOpcode = ISD::FNEG;
12412 // Fold (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X
12414 // fneg (fabs X)
12423 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp);
12501 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
12505 // fold (bitcast (fneg x)) ->
12513 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
12526 if (N0.getOpcode() == ISD::FNEG) {
12545 if (N0.getOpcode() == ISD::FNEG)
[all...] |
| LegalizeVectorOps.cpp | 406 case ISD::FNEG:
766 case ISD::FNEG:
1329 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1338 // For floating-point values, (a-b) is the same as a+(-b). If FNEG is legal,
1342 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
|
| LegalizeFloatTypes.cpp | 100 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break;
477 // Expand Y = FNEG(X) -> Y = X ^ sign mask
1219 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break;
1310 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo),
1475 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo);
1476 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi);
2237 case ISD::FNEG:
2601 case ISD::FNEG:
|
| SelectionDAGBuilder.h | 685 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); }
|
| SelectionDAGDumper.cpp | 194 case ISD::FNEG: return "fneg";
|
| LegalizeDAG.cpp | 1567 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1569 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
3123 case ISD::FNEG:
3232 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3234 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3819 SDValue Neg = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(2), Flags);
4734 case ISD::FNEG:
|
| FastISel.cpp | 1598 /// Emit an FNeg operation.
1604 // If the target has ISD::FNEG, use it.
1606 Register ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1720 case Instruction::FNeg:
|
| SelectionDAG.cpp | 4310 case ISD::FNEG:
4680 case ISD::FNEG:
4752 case ISD::FNEG:
4987 case ISD::FNEG:
4992 if (OpOpcode == ISD::FNEG) // --X -> X
4996 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
5425 // -0.0 - undef --> undef (consistent with "fneg undef")
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 617 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
622 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
788 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
789 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
829 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/
830 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/
935 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/
936 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/
937 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/
938 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org
[all...] |
| /src/sys/arch/sparc/fpu/ |
| fpu.c | 465 case FNEG >> 2:
466 DPRINTF(FPE_INSN, ("fpu_execute: FNEG\n"));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1621 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1728 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1731 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1750 setOperationAction(ISD::FNEG, MVT::f128, Custom);
2702 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2704 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2705 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2846 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS
[all...] |
| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativeARM_64.c | 92 #define FNEG 0x1e614000
1714 FAIL_IF(push_inst(compiler, (FNEG ^ inv_bits) | VD(dst_r) | VN(src)));
|
| sljitNativePPC_common.c | 178 #define FNEG (HI(63) | LO(40))
1933 FAIL_IF(push_inst(compiler, FNEG | FD(dst_r) | FB(src)));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 763 setOperationAction(ISD::FNEG, VT, Custom);
2380 case ISD::FNEG:
5543 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5545 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
5554 if (Op0.getOpcode() == ISD::FNEG) {
5717 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5719 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
5725 if (Op0.getOpcode() == ISD::FNEG)
5851 // operand. Try and bubble any FNEG up after the extend/round to produce
5856 // those is typically more expensive than removing a fneg
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 1754 case FNeg: return ISD::FNEG;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 527 setOperationAction(ISD::FNEG, MVT::f16, Expand);
528 setOperationAction(ISD::FNEG, MVT::v2f16, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 793 setOperationAction(ISD::FNEG, VT, Expand);
1073 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1211 setOperationAction(ISD::FNEG, MVT::f128, Expand);
7853 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
7872 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
7889 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
9204 // for fneg/fabs.
16366 // (fneg (fnmsub a b c)) => (fnmsub (fneg a) b (fneg c)
[all...] |
