| /src/bin/pax/ |
| options.c | 157 FSUB fsub[] = { variable
286 FSUB tmp;
481 frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub,
482 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt);
489 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i
[all...] |
| pax.h | 225 } FSUB;
|
| extern.h | 200 extern FSUB fsub[];
227 extern FSUB *frmt;
|
| pax.c | 77 FSUB *frmt = NULL; /* archive format type */
|
| ar_subs.c | 759 FSUB *orgfrmt;
1352 if (fsub[ford[i]].hsz < minhd)
1353 minhd = fsub[ford[i]].hsz;
1404 if ((*fsub[ford[i]].id)(hdbuf, hdsz) < 0)
1406 frmt = &(fsub[ford[i]]);
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| rx-parse.h | 123 FSUB = 324, /* FSUB */
292 #define FSUB 324
|
| rx-parse.y | 161 %token FADD FCMP FDIV FMUL FREIT FSUB FSQRT FTOD FTOI FTOU
674 | FSUB { sub_op = 0; } float3_op
1395 OPC(FSUB),
|
| rx-parse.c | 305 FSUB = 324, /* FSUB */
474 #define FSUB 324
668 YYSYMBOL_FSUB = 69, /* FSUB */
1326 "EMULU", "FADD", "FCMP", "FDIV", "FMUL", "FREIT", "FSUB", "FSQRT",
4741 OPC(FSUB),
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| rx-parse.h | 123 FSUB = 324, /* FSUB */
292 #define FSUB 324
|
| rx-parse.y | 161 %token FADD FCMP FDIV FMUL FREIT FSUB FSQRT FTOD FTOI FTOU
674 | FSUB { sub_op = 0; } float3_op
1395 OPC(FSUB),
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 372 FSUB,
|
| /src/sys/arch/m68k/m68k/ |
| db_disasm.h | 374 #define FSUB ENCFT(1,0,1,0,0,0)
|
| /src/sys/arch/sparc/include/ |
| instr.h | 411 #define FSUB 0x44
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 375 case ISD::FSUB:
769 case ISD::FSUB:
1326 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Node->getValueType(0))) {
1329 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1330 return DAG.getNode(ISD::FSUB, DL, Node->getValueType(0), Zero,
|
| SelectionDAGBuilder.cpp | 4620 case AtomicRMWInst::FSub: NT = ISD::ATOMIC_LOAD_FSUB; break;
4914 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
5051 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5068 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5074 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5093 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5099 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5105 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5147 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5164 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2
[all...] |
| SelectionDAGBuilder.h | 692 void visitFSub(const User &I) { visitBinary(I, ISD::FSUB); }
|
| SelectionDAGDumper.cpp | 254 case ISD::FSUB: return "fsub";
|
| LegalizeFloatTypes.cpp | 123 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
1238 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
2256 case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break;
2621 case ISD::FSUB: R = SoftPromoteHalfRes_BinOp(N); break;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 232 { ISD::FSUB, MVT::v2f64, 2 }, // subpd
619 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
624 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
792 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
793 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
854 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
855 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/
856 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
857 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
943 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org
[all...] |
| X86IntrinsicsInfo.h | 916 X86_INTRINSIC_DATA(avx512_sub_pd_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
917 X86_INTRINSIC_DATA(avx512_sub_ps_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
|
| /src/sys/arch/sparc/fpu/ |
| fpu.c | 498 case FSUB >> 2:
499 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n"));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUTargetTransformInfo.cpp | 622 // Check possible fuse {fadd|fsub}(a,fmul(b,c)) and return zero cost for
623 // fmul(b,c) supposing the fadd|fsub will get estimated cost for the whole
628 if (OPC == ISD::FADD || OPC == ISD::FSUB) {
644 case ISD::FSUB:
|
| AMDGPUISelLowering.cpp | 320 setOperationAction(ISD::FSUB, MVT::f64, Expand);
483 setOperationAction(ISD::FSUB, VT, Expand);
560 setTargetDAGCombine(ISD::FSUB);
587 case ISD::FSUB:
2214 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2249 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
4723 case AtomicRMWInst::FSub:
|
| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativeARM_64.c | 93 #define FSUB 0x1e603800
1761 FAIL_IF(push_inst(compiler, (FSUB ^ inv_bits) | VD(dst_r) | VN(src1) | VM(src2)));
|
| sljitNativePPC_common.c | 180 #define FSUB (HI(63) | LO(20))
1865 FAIL_IF(push_inst(compiler, FSUB | FD(dst_r) | FA(TMP_FREG1) | FB(TMP_FREG2)));
2005 FAIL_IF(push_inst(compiler, SELECT_FOP(op, FSUBS, FSUB) | FD(dst_r) | FA(src1) | FB(src2)));
|
