| /src/external/gpl3/binutils/dist/opcodes/ |
| s390-opc.c | 97 #define F_24 (F_16 + 1) /* FPR starting at position 24 */
99 #define F_28 (F_24 + 1) /* FPR starting at position 28 */
346 #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. lzer */
348 #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
350 #define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */
359 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
361 #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
362 #define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */
363 #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */
364 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr *
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| s390-opc.c | 97 #define F_24 (F_16 + 1) /* FPR starting at position 24 */
99 #define F_28 (F_24 + 1) /* FPR starting at position 28 */
346 #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. lzer */
348 #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
350 #define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */
359 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
361 #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
362 #define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */
363 #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */
364 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr *
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| s390-opc.c | 97 #define F_24 (F_16 + 1) /* FPR starting at position 24 */
99 #define F_28 (F_24 + 1) /* FPR starting at position 28 */
346 #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. lzer */
348 #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
350 #define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */
359 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
361 #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
362 #define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */
363 #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */
364 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr *
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| s390-opc.c | 95 #define F_24 (F_16 + 1) /* FPR starting at position 24 */
97 #define F_28 (F_24 + 1) /* FPR starting at position 28 */
356 #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. lzer */
358 #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
360 #define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */
369 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
371 #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
372 #define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */
373 #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */
374 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr *
[all...] |
