| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 75 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
80 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
85 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
88 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
91 static DecodeStatus Decode2RInstruction(MCInst &Inst,
96 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
101 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
106 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
111 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
116 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCInstrAnalysis.h | 37 virtual bool isBranch(const MCInst &Inst) const {
38 return Info->get(Inst.getOpcode()).isBranch();
41 virtual bool isConditionalBranch(const MCInst &Inst) const {
42 return Info->get(Inst.getOpcode()).isConditionalBranch();
45 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
46 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
49 virtual bool isIndirectBranch(const MCInst &Inst) const {
50 return Info->get(Inst.getOpcode()).isIndirectBranch();
53 virtual bool isCall(const MCInst &Inst) const {
54 return Info->get(Inst.getOpcode()).isCall()
[all...] |
| MCInstBuilder.h | 22 MCInst Inst;
27 Inst.setOpcode(Opcode);
32 Inst.addOperand(MCOperand::createReg(Reg));
38 Inst.addOperand(MCOperand::createImm(Val));
44 Inst.addOperand(MCOperand::createSFPImm(Val));
50 Inst.addOperand(MCOperand::createDFPImm(Val));
56 Inst.addOperand(MCOperand::createExpr(Val));
62 Inst.addOperand(MCOperand::createInst(Val));
68 Inst.addOperand(Op);
73 return Inst;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
76 Inst.addOperand(MCOperand::createImm(Offset));
84 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
87 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
91 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
94 return decodeRegisterClass(Inst, RegNo, CRRegs);
97 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
100 return decodeRegisterClass(Inst, RegNo, CRBITRegs)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 82 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
88 Inst.addOperand(MCOperand::createReg(RegNo));
92 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
95 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
98 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
101 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
104 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
107 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
110 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
113 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCELFStreamer.cpp | 48 void PPCELFStreamer::emitPrefixedInstruction(const MCInst &Inst,
64 // also forces the addition of a new fragment. Inst is now the first
66 MCELFStreamer::emitInstruction(Inst, STI);
71 SMLoc InstLoc = Inst.getLoc();
88 void PPCELFStreamer::emitInstruction(const MCInst &Inst,
97 Optional<bool> IsPartOfGOTToPCRelPair = isPartOfGOTToPCRelPair(Inst, STI);
104 emitGOTToPCRelReloc(Inst);
107 if (!Emitter->isPrefixedInstruction(Inst)) {
108 MCELFStreamer::emitInstruction(Inst, STI);
111 emitPrefixedInstruction(Inst, STI)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVMatInt.h | 19 struct Inst {
23 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
25 using InstSeq = SmallVector<Inst, 8>;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/ |
| M68kAsmBackend.cpp | 68 bool mayNeedRelaxation(const MCInst &Inst,
75 void relaxInstruction(MCInst &Inst,
97 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst) {
98 unsigned Op = Inst.getOpcode();
135 static unsigned getRelaxedOpcodeArith(const MCInst &Inst) {
136 unsigned Op = Inst.getOpcode();
141 static unsigned getRelaxedOpcode(const MCInst &Inst) {
142 unsigned R = getRelaxedOpcodeArith(Inst);
143 if (R != Inst.getOpcode())
145 return getRelaxedOpcodeBranch(Inst);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| PseudoProbe.cpp | 24 Optional<PseudoProbe> extractProbeFromDiscriminator(const Instruction &Inst) {
25 assert(isa<CallBase>(&Inst) && !isa<IntrinsicInst>(&Inst) &&
28 if (const DebugLoc &DLoc = Inst.getDebugLoc()) {
48 Optional<PseudoProbe> extractProbe(const Instruction &Inst) {
49 if (const auto *II = dyn_cast<PseudoProbeInst>(&Inst)) {
59 if (isa<CallBase>(&Inst) && !isa<IntrinsicInst>(&Inst))
60 return extractProbeFromDiscriminator(Inst);
65 void setProbeDistributionFactor(Instruction &Inst, float Factor)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
65 static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst,
69 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 82 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
87 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
97 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
102 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
107 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
112 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
117 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
122 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
127 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| CFLGraph.h | 263 void visitReturnInst(ReturnInst &Inst) {
264 if (auto RetVal = Inst.getReturnValue()) {
272 void visitPtrToIntInst(PtrToIntInst &Inst) {
273 auto *Ptr = Inst.getOperand(0);
277 void visitIntToPtrInst(IntToPtrInst &Inst) {
278 auto *Ptr = &Inst;
282 void visitCastInst(CastInst &Inst) {
283 auto *Src = Inst.getOperand(0);
284 addAssignEdge(Src, &Inst);
287 void visitFreezeInst(FreezeInst &Inst) {
[all...] |
| PHITransAddr.cpp | 25 static bool CanPHITrans(Instruction *Inst) {
26 if (isa<PHINode>(Inst) ||
27 isa<GetElementPtrInst>(Inst))
30 if (isa<CastInst>(Inst) &&
31 isSafeToSpeculativelyExecute(Inst))
34 if (Inst->getOpcode() == Instruction::Add &&
35 isa<ConstantInt>(Inst->getOperand(1)))
117 Instruction *Inst = dyn_cast<Instruction>(Addr);
118 return !Inst || CanPHITrans(Inst);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 20 const MCInst &Inst,
26 bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
33 MCInstrAnalysis::evaluateMemoryOperandAddress(const MCInst &Inst, uint64_t Addr,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/ |
| RISCVDisassembler.cpp | 61 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
74 Inst.addOperand(MCOperand::createReg(Reg));
78 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo,
85 Inst.addOperand(MCOperand::createReg(Reg));
89 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
96 Inst.addOperand(MCOperand::createReg(Reg));
100 static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
107 Inst.addOperand(MCOperand::createReg(Reg));
111 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
118 Inst.addOperand(MCOperand::createReg(Reg))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| VPlanTransforms.cpp | 37 Instruction *Inst = cast<Instruction>(VPV->getUnderlyingValue());
38 if (DeadInstructions.count(Inst)) {
60 assert(!isa<PHINode>(Inst) && "phis should be handled above");
62 if (LoadInst *Load = dyn_cast<LoadInst>(Inst)) {
64 *Load, Plan->getOrAddVPValue(getLoadStorePointerOperand(Inst)),
66 } else if (StoreInst *Store = dyn_cast<StoreInst>(Inst)) {
68 *Store, Plan->getOrAddVPValue(getLoadStorePointerOperand(Inst)),
71 } else if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Inst)) {
74 } else if (CallInst *CI = dyn_cast<CallInst>(Inst)) {
77 } else if (SelectInst *SI = dyn_cast<SelectInst>(Inst)) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiMCCodeEmitter.cpp | 51 uint64_t getBinaryCodeForInstr(const MCInst &Inst,
57 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
61 unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo,
65 unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo,
69 unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo,
73 unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo,
77 void encodeInstruction(const MCInst &Inst, raw_ostream &Ostream,
81 unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
84 unsigned adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
110 const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/ObjCARC/ |
| DependencyAnalysis.h | 61 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg,
66 bool CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA,
71 bool CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
74 /// Returns true if we can not conservatively prove that Inst can not decrement
76 bool CanDecrementRefCount(const Instruction *Inst, const Value *Ptr,
79 static inline bool CanDecrementRefCount(const Instruction *Inst,
82 return CanDecrementRefCount(Inst, Ptr, PA, GetARCInstKind(Inst));
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-reduce/deltas/ |
| ReduceInstructions.cpp | 31 for (auto &Inst : make_range(BB.begin(), std::prev(BB.end())))
33 InstToKeep.insert(&Inst);
39 for (auto &Inst : BB)
40 if (!InstToKeep.count(&Inst)) {
41 Inst.replaceAllUsesWith(UndefValue::get(Inst.getType()));
42 InstToDelete.push_back(&Inst);
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| Sink.cpp | 35 static bool isSafeToMove(Instruction *Inst, AliasAnalysis &AA,
38 if (Inst->mayWriteToMemory()) {
39 Stores.insert(Inst);
43 if (LoadInst *L = dyn_cast<LoadInst>(Inst)) {
50 if (Inst->isTerminator() || isa<PHINode>(Inst) || Inst->isEHPad() ||
51 Inst->mayThrow())
54 if (auto *Call = dyn_cast<CallBase>(Inst)) {
70 static bool IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst,
198 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo
[all...] |
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| InstrInfoEmitter.cpp | 76 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
101 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
119 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
122 for (auto &Op : Inst.Operands) {
215 for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
216 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
241 for (const CodeGenInstruction *Inst : NumberedInstructions) {
242 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
245 for (const auto &Info : Inst->Operands) {
255 Inst->TheDef->getName().str())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.h | 19 struct Inst {
22 Inst(unsigned Opc, unsigned ImmOpnd);
24 using InstSeq = SmallVector<Inst, 7>;
35 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/Disassembler/ |
| AVRDisassembler.cpp | 71 static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo,
77 Inst.addOperand(MCOperand::createReg(Register));
81 static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
87 Inst.addOperand(MCOperand::createReg(Register));
91 static DecodeStatus DecodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo,
98 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn,
101 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn,
104 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn,
107 static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
110 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86InstComments.cpp | 25 #define CASE_SSE_INS_COMMON(Inst, src) \
26 case X86::Inst##src:
28 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
29 case X86::V##Inst##Suffix##src:
31 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
32 case X86::V##Inst##Suffix##src##k:
34 #define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \
35 case X86::V##Inst##Suffix##src##kz:
37 #define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
38 CASE_AVX_INS_COMMON(Inst, Suffix, src)
[all...] |
