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    Searched refs:LoHalf (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAGHVX.cpp 627 return OpRef(R.OpN & (Undef | Index | LoHalf));
647 LoHalf = 0x20000000,
649 Whole = LoHalf | HiHalf,
724 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf);
725 if (OpN & LoHalf)
991 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf);
994 unsigned Sub = (Part == OpRef::LoHalf) ? Hexagon::vsub_lo
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 1700 MachineInstr *LoHalf =
1706 (void)LoHalf;
1707 LLVM_DEBUG(dbgs() << " "; LoHalf->dump(););
SIInstrInfo.cpp 6350 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
6370 Worklist.insert(&LoHalf);
6419 MachineInstr *LoHalf =
6445 legalizeOperands(*LoHalf, MDT);
6491 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
6509 Worklist.insert(&LoHalf);
SIISelLowering.cpp 3988 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
4008 TII->legalizeOperands(*LoHalf);
5412 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
5417 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf);
5431 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf });
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 4823 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass);
4832 .addDef(LoHalf)
4840 .addUse(LoHalf);

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