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    Searched refs:Load0 (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 129 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
132 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
135 unsigned Opc0 = Load0->getMachineOpcode();
145 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
149 if (Load0->getOperand(0) != Load1->getOperand(0))
166 Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue();
177 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
180 if (Load0->getOperand(0) != Load1->getOperand(0))
184 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
200 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) |
    [all...]
SIInstrInfo.h 198 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
AMDGPURegisterBankInfo.cpp 1191 auto Load0 = B.buildLoadFromOffset(Part64, PtrReg, *MMO, 0);
1195 auto Ins0 = B.buildInsert(LoadTy, Undef, Load0, 0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLoweringHVX.cpp 1828 SDValue Load0 = DAG.getLoad(SingleTy, dl, Chain, Base0, MOp0);
1831 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1),
1833 Load0.getValue(1), Load1.getValue(1)) }, dl);
HexagonISelLowering.cpp 3022 SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO);
3026 {Load1, Load0, BaseNoOff.getOperand(0)});
3028 Load0.getValue(1), Load1.getValue(1));

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