| /src/sys/external/bsd/drm2/include/linux/ |
| bitfield.h | 34 #define FIELD_GET(MASK, VAR) __SHIFTOUT(VAR, MASK)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| gk20a.h | 32 #define MASK(w) ((1 << (w)) - 1)
51 (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT)
61 (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT)
89 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
94 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
96 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
97 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
|
| nouveau_nvkm_subdev_clk_gm20b.c | 46 (MASK(GPCPLL_CFG2_SDM_DIN_WIDTH) << GPCPLL_CFG2_SDM_DIN_SHIFT)
50 (MASK(GPCPLL_CFG2_SDM_DIN_NEW_WIDTH) << GPCPLL_CFG2_SDM_DIN_NEW_SHIFT)
58 (MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH) << GPCPLL_DVFS0_DFS_COEFF_SHIFT)
62 (MASK(GPCPLL_DVFS0_DFS_DET_MAX_WIDTH) << GPCPLL_DVFS0_DFS_DET_MAX_SHIFT)
174 MASK(GPCPLL_CFG2_SDM_DIN_WIDTH);
206 dvfs->dfs_coeff = min_t(u32, coeff, MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH));
259 rem = ((u32)n) & MASK(DFS_DET_RANGE);
264 *sdm_din = (rem >> BITS_PER_BYTE) & MASK(GPCPLL_CFG2_SDM_DIN_WIDTH);
541 nvkm_mask(device, GPC_BCAST_GPCPLL_DVFS2, MASK(DFS_DET_RANGE + 1),
793 data &= MASK(GPCPLL_CFG3_PLL_DFS_TESTOUT_WIDTH)
[all...] |
| nouveau_nvkm_subdev_clk_gk20a.c | 76 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
77 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
78 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
87 val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT;
88 val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
89 val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT;
|
| /src/lib/libm/src/ |
| s_modfl.c | 55 #define MASK ((uint64_t)-1)
57 #define MASK ((uint32_t)-1)
60 #define GETFRAC(bits, n) ((bits) & ~(MASK << (n)))
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_hw_gpio.c | 50 REG_GET(MASK_reg, MASK, &gpio->store.mask);
59 REG_UPDATE(MASK_reg, MASK, gpio->store.mask);
155 * program the pin as GPIO, mask out signal driven by HW */
157 REG_UPDATE(MASK_reg, MASK, 1);
161 * program the pin as GPIO, mask out signal driven by HW */
163 REG_UPDATE(MASK_reg, MASK, 1);
169 REG_UPDATE(MASK_reg, MASK, 1);
173 REG_UPDATE(MASK_reg, MASK, 0)
[all...] |
| generic_regs.h | 40 GENERIC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\
|
| ddc_regs.h | 43 DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
66 DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\
83 DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\
|
| hpd_regs.h | 48 HPD_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
|
| /src/usr.bin/nfsstat/ |
| nfsstat.c | 77 #define MASK(a) (1 << NFSPROC_##a)
79 (MASK(GETATTR) | MASK(SETATTR) | MASK(LOOKUP) | MASK(READ) | \
80 MASK(WRITE) | MASK(RENAME)| MASK(ACCESS) | MASK(READDIR) | \
81 MASK(READDIRPLUS)
84 int mask; member in struct:shortprocs
411 int mask = shortprocs[i].mask; local in function:sidewaysintpr
[all...] |
| /src/sys/dev/pci/ |
| pvscsi.h | 66 #define MASK(v) ((1 << (v)) - 1)
149 #define PVSCSI_FLAG_RESERVED_MASK (~MASK(5))
153 #define PVSCSI_INTR_CMPL_MASK MASK(2)
157 #define PVSCSI_INTR_MSG_MASK (MASK(2) << 2)
159 #define PVSCSI_INTR_ALL_SUPPORTED MASK(4)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_cursor.c | 51 MASK(NV_CIO_CRE_HCUR_ASI) |
57 MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
|
| hw.h | 33 #define MASK(field) ( \
37 (((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield))
304 /* 0xfa is generic "unlock all" mask */
381 *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
383 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
394 int mask; local in function:nv_pitch_align
403 mask = 128 / bpp - 1;
405 mask = 512 / bpp - 1;
407 return (width + mask) & ~mask;
[all...] |
| nouveau_dispnv04_crtc.c | 363 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
393 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
737 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
|
| /src/sbin/ifconfig/ |
| extern.h | 39 #define MASK 2
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_syncmap.c | 38 #define MASK (KSYNCMAP - 1)
119 return (id >> p->height) & MASK;
126 return id & MASK;
310 idx = p->prefix >> (above - SHIFT) & MASK;
|
| /src/usr.sbin/ipwctl/ |
| ipwctl.c | 149 #define MASK HEX
301 { 180, "Channels supported for this country", MASK },
314 { 193, "Supported transmission rates", MASK },
316 { 195, "Supported basic transmission rates", MASK },
|
| /src/lib/libc/rpc/ |
| xdr_float.c | 196 #define MASK(nbits) ((1 << nbits) - 1)
261 id.mantissa2 = ((vd.mantissa2 & MASK(3)) << 29) |
263 (((unsigned int)vd.mantissa4 >> 3) & MASK(13));
303 vd.mantissa2 = ((id.mantissa1 & MASK(13)) << 3) |
|
| /src/sys/dev/microcode/aic7xxx/ |
| aicasm_symbol.h | 59 MASK,
89 uint8_t mask; member in struct:field_info
|
| aicasm_symbol.c | 108 case MASK:
244 case MASK:
364 " uint8_t mask;\n"
457 curnode->symbol->info.finfo->mask);
501 case MASK:
619 case MASK:
|
| aicasm_gram.y | 90 static void process_field(int field_type, symbol_t *sym, int mask);
317 * with no bit or mask definitions.
503 process_field(MASK, $2, $3.value);
682 case MASK:
1395 if (field_type != MASK && value == 0) {
1400 sym->info.finfo->mask = value;
1402 sym->info.finfo->mask = field_symbol->info.finfo->value;
1404 sym->info.finfo->mask = 0xFF;
1422 cur_symbol->info.rinfo->valid_bitmask |= sym->info.finfo->mask;
1469 case MASK
[all...] |
| /src/sys/dev/ic/ |
| i128.c | 78 bus_space_write_4(tag, regh, MASK, 0xffffffff);
|
| i128reg.h | 153 #define MASK 0x4070
|
| /src/sys/external/bsd/drm2/dist/drm/i915/selftests/ |
| i915_syncmap.c | 419 u64 context = i915_prandom_u64_state(&prng) & ~MASK;
|
| /src/sys/uvm/ |
| uvm_fault.c | 714 #define MASK(entry) (UVM_ET_ISCOPYONWRITE(entry) ? \
1999 flt->access_type & MASK(ufi->entry), ufi->entry->advice,
2099 flt->enter_prot & MASK(ufi->entry);
2133 access_type = flt->access_type & MASK(ufi->entry);
|
