| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86ATTInstPrinter.h | 27 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
29 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
33 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
39 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
40 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &OS);
43 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
44 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
45 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
46 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O)
[all...] |
| X86InstPrinterCommon.h | 25 virtual void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) = 0;
26 void printCondCode(const MCInst *MI, unsigned Op, raw_ostream &OS);
27 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
28 void printVPCOMMnemonic(const MCInst *MI, raw_ostream &OS);
29 void printVPCMPMnemonic(const MCInst *MI, raw_ostream &OS);
30 void printCMPMnemonic(const MCInst *MI, bool IsVCmp, raw_ostream &OS);
31 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &O);
32 void printPCRelImm(const MCInst *MI, uint64_t Address, unsigned OpNo,
36 void printInstFlags(const MCInst *MI, raw_ostream &O);
37 void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O)
[all...] |
| X86IntelInstPrinter.h | 28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
30 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
34 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
35 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
40 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
41 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
44 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override;
45 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
46 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
47 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
[all...] |
| X86InstComments.cpp | 249 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize,
251 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
260 static void printMasking(raw_ostream &OS, const MCInst *MI,
262 const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
274 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg());
284 static bool printFMAComments(const MCInst *MI, raw_ostream &OS,
287 unsigned NumOperands = MI->getNumOperands();
306 switch (MI->getOpcode()) {
312 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
316 Mul2Name = getRegName(MI->getOperand(2).getReg())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| LostDebugLocObserver.cpp | 33 for (MachineInstr *MI : PotentialMIsForDebugLocs) {
34 if (!MI->getDebugLoc())
38 if (MI->getDebugLoc().getLine() == 0) {
43 if (LostDebugLocs.erase(MI->getDebugLoc())) {
44 LOC_DEBUG(dbgs() << ".. .. found " << MI->getDebugLoc() << " in " << *MI);
45 FoundIn.insert(MI);
61 for (MachineInstr *MI : FoundIn)
62 if (PotentialMIsForDebugLocs.erase(MI))
63 dbgs() << ".. .. " << *MI;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/ |
| M68kInstPrinter.h | 30 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
34 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
37 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
38 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
41 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
44 void printOperand(const MCInst *MI, unsigned opNum, raw_ostream &O);
45 void printImmediate(const MCInst *MI, unsigned opNum, raw_ostream &O);
47 void printMoveMask(const MCInst *MI, unsigned opNum, raw_ostream &O);
49 void printMoveMaskR(const MCInst *MI, unsigned opNum, raw_ostream &O);
50 void printDisp(const MCInst *MI, unsigned opNum, raw_ostream &O)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsInstPrinter.cpp | 31 static bool isReg(const MCInst &MI, unsigned OpNo) {
32 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
33 return MI.getOperand(OpNo).getReg() == R;
78 void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address,
81 switch (MI->getOpcode()) {
91 printSaveRestore(MI, O);
96 printSaveRestore(MI, O);
101 printSaveRestore(MI, O);
106 printSaveRestore(MI, O);
112 if (!printAliasInstr(MI, Address, O) && !printAlias(*MI, O)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| CombinerHelper.h | 43 MachineInstr *MI;
122 /// If \p MI is COPY, try to combine it.
123 /// Returns true if MI changed.
124 bool tryCombineCopy(MachineInstr &MI);
125 bool matchCombineCopy(MachineInstr &MI);
126 void applyCombineCopy(MachineInstr &MI);
140 /// If \p MI is extend that consumes the result of a load, try to combine it.
141 /// Returns true if MI changed.
142 bool tryCombineExtendingLoads(MachineInstr &MI);
143 bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo)
[all...] |
| LegalizerHelper.h | 74 /// Replace \p MI by a sequence of legal instructions that can implement the
75 /// same operation. Note that this means \p MI may be deleted, so any iterator
77 /// be initialized to the MachineFunction containing \p MI.
80 /// registers as \p MI.
81 LegalizeResult legalizeInstrStep(MachineInstr &MI);
84 LegalizeResult libcall(MachineInstr &MI);
88 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
93 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
96 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
100 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCBranchFinalize.cpp | 51 void replaceWithBRcc(MachineInstr *MI) const;
52 void replaceWithCmpBcc(MachineInstr *MI) const;
95 static bool isBRccPseudo(MachineInstr *MI) {
96 return !(MI->getOpcode() != ARC::BRcc_rr_p &&
97 MI->getOpcode() != ARC::BRcc_ru6_p);
100 static unsigned getBRccForPseudo(MachineInstr *MI) {
101 assert(isBRccPseudo(MI) && "Can't get BRcc for wrong instruction.");
102 if (MI->getOpcode() == ARC::BRcc_rr_p)
107 static unsigned getCmpForPseudo(MachineInstr *MI) {
108 assert(isBRccPseudo(MI) && "Can't get BRcc for wrong instruction.")
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZShortenInst.cpp | 43 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
44 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
45 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
46 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
47 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
48 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
49 bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode);
66 // Tie operands if MI has become a two-address instruction.
67 static void tieOpsIfNeeded(MachineInstr &MI) {
68 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZInstPrinter.cpp | 70 void SystemZInstPrinter::printInst(const MCInst *MI, uint64_t Address,
73 printInstruction(MI, Address, O);
78 static void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {
79 int64_t Value = MI->getOperand(OpNum).getImm();
85 static void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {
86 int64_t Value = MI->getOperand(OpNum).getImm();
91 void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum,
93 printUImmOperand<1>(MI, OpNum, O);
96 void SystemZInstPrinter::printU2ImmOperand(const MCInst *MI, int OpNum,
98 printUImmOperand<2>(MI, OpNum, O)
[all...] |
| SystemZMCCodeEmitter.cpp | 47 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
53 uint64_t getBinaryCodeForInstr(const MCInst &MI,
58 // MO in MI. Fixups is the list of fixups against MI.
59 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
67 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
70 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
73 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
76 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
79 uint64_t getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMOptimizeBarriersPass.cpp | 40 // The current implementation allows this iif MI does not have any possible
42 static bool CanMovePastDMB(const MachineInstr *MI) {
43 return !(MI->mayLoad() ||
44 MI->mayStore() ||
45 MI->hasUnmodeledSideEffects() ||
46 MI->isCall() ||
47 MI->isReturn());
66 for (auto &MI : MBB) {
67 if (MI.getOpcode() == ARM::DMB) {
71 if (MI.getOperand(0).getImm() == DMBType)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/MCTargetDesc/ |
| VEInstPrinter.cpp | 47 void VEInstPrinter::printInst(const MCInst *MI, uint64_t Address,
50 if (!printAliasInstr(MI, Address, STI, OS))
51 printInstruction(MI, Address, STI, OS);
55 void VEInstPrinter::printOperand(const MCInst *MI, int OpNum,
57 const MCOperand &MO = MI->getOperand(OpNum);
65 switch (MI->getOpcode()) {
78 void VEInstPrinter::printMemASXOperand(const MCInst *MI, int OpNum,
83 printOperand(MI, OpNum, STI, O);
85 printOperand(MI, OpNum + 1, STI, O);
89 if (MI->getOperand(OpNum + 2).isImm() &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
201 /// into real instructions. The target can edit MI in place, or it can insert
202 /// new instructions and erase MI. The function should return true if
204 bool expandPostRAPseudo(MachineInstr &MI) const override;
220 MachineBasicBlock::iterator MI) const override;
223 bool isPredicated(const MachineInstr &MI) const override;
226 bool isPostIncrement(const MachineInstr &MI) const override
[all...] |
| HexagonDepDecoders.inc | 16 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
18 signedDecoder<6>(MI, tmp, Decoder);
21 static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp,
23 signedDecoder<12>(MI, tmp, Decoder);
26 static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp,
28 signedDecoder<13>(MI, tmp, Decoder);
31 static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp,
33 signedDecoder<14>(MI, tmp, Decoder);
36 static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
38 signedDecoder<3>(MI, tmp, Decoder)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 51 bool LowerSubregToReg(MachineInstr *MI);
52 bool LowerCopy(MachineInstr *MI);
54 void TransferImplicitOperands(MachineInstr *MI);
64 /// TransferImplicitOperands - MI is a pseudo-instruction, and the lowered
66 /// operands from MI to the replacement instruction.
67 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) {
68 MachineBasicBlock::iterator CopyMI = MI;
71 for (const MachineOperand &MO : MI->implicit_operands())
76 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
77 MachineBasicBlock *MBB = MI->getParent()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMInstPrinter.h | 28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
33 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
34 void printInstruction(const MCInst *MI, uint64_t Address,
36 virtual bool printAliasInstr(const MCInst *MI, uint64_t Address,
38 virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
45 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
47 void printOperand(const MCInst *MI, uint64_t /*Address*/, unsigned OpNum,
49 printOperand(MI, OpNum, STI, O);
52 void printSORegRegOperand(const MCInst *MI, unsigned OpNum,
54 void printSORegImmOperand(const MCInst *MI, unsigned OpNum
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiInstPrinter.cpp | 38 bool LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
42 printOperand(MI, OpNo0, OS);
44 printOperand(MI, OpNo1, OS);
48 static bool usesGivenOffset(const MCInst *MI, int AddOffset) {
49 unsigned AluCode = MI->getOperand(3).getImm();
51 (MI->getOperand(2).getImm() == AddOffset ||
52 MI->getOperand(2).getImm() == -AddOffset);
55 static bool isPreIncrementForm(const MCInst *MI, int AddOffset) {
56 unsigned AluCode = MI->getOperand(3).getImm();
57 return LPAC::isPreOp(AluCode) && usesGivenOffset(MI, AddOffset)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InsertWait.cpp | 65 static bool isX87Instruction(MachineInstr &MI) {
66 for (const MachineOperand &MO : MI.operands()) {
75 static bool isX87ControlInstruction(MachineInstr &MI) {
76 switch (MI.getOpcode()) {
99 static bool isX87NonWaitingControlInstruction(MachineInstr &MI) {
101 switch (MI.getOpcode()) {
122 for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
124 if (!isX87Instruction(*MI))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPULegalizerInfo.h | 39 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
45 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
60 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI
[all...] |
| GCNHazardRecognizer.cpp | 47 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) {
48 CurrCycleInstr = MI;
97 static bool isXDL(const GCNSubtarget &ST, const MachineInstr &MI) {
98 unsigned Opcode = MI.getOpcode();
100 if (!SIInstrInfo::isMAI(MI) ||
110 const MachineInstr &MI) {
111 if (TII.isAlwaysGDS(MI.getOpcode()))
114 switch (MI.getOpcode()) {
125 if (TII.isDS(MI.getOpcode())) {
126 int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64InstPrinter.h | 28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
33 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
34 virtual void printInstruction(const MCInst *MI, uint64_t Address,
36 virtual bool printAliasInstr(const MCInst *MI, uint64_t Address,
38 virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
51 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
54 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
56 void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
58 void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
61 void printSImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCInstPrinter.h | 35 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
39 std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
40 void printInstruction(const MCInst *MI, uint64_t Address,
44 bool printAliasInstr(const MCInst *MI, uint64_t Address,
46 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
50 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
52 void printPredicateOperand(const MCInst *MI, unsigned OpNo,
55 void printATBitsAsHint(const MCInst *MI, unsigned OpNo,
58 void printU1ImmOperand(const MCInst *MI, unsigned OpNo,
60 void printU2ImmOperand(const MCInst *MI, unsigned OpNo
[all...] |
