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| /src/sys/arch/mips/cavium/dev/ | |
| octeon_uartreg.h | 95 #define MIO_UART0_BASE 0x0001180000000800ULL |
| octeon_uart.c | 67 MIO_UART0_BASE, |
| /src/sys/arch/mips/cavium/ | |
| octeon1p_iobus.c | 47 .addr = MIO_UART0_BASE |