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  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
pll.h 11 int *N1, int *M1, int *N2, int *M2, int *P);
nouveau_nvkm_subdev_clk_nv04.c 40 int N1, M1, N2, M2, P;
41 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P);
44 pv->N1 = N1;
nouveau_nvkm_subdev_clk_nv40.c 68 int N1 = (coef & 0x0000ff00) >> 8;
74 khz = ref * N1 / M1;
130 int *N1, int *M1, int *N2, int *M2, int *log2P)
143 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
156 int N1, M1, N2, M2, log2P;
161 &N1, &M1, &N2, &M2, &log2P);
167 clk->npll_coef = (N1 << 8) | M1;
170 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
176 &N1, &M1, NULL, NULL, &log2P);
180 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1
    [all...]
nouveau_nvkm_subdev_clk_pllnv04.c 156 int M1, N1, M2, N2, log2P;
175 for (N1 = minN1; N1 <= maxN1; N1++) {
176 calcclk1 = crystal * N1 / M1;
216 *pN1 = N1;
233 int *N1, int *M1, int *N2, int *M2, int *P)
238 ret = getMNP_single(subdev, info, freq, N1, M1, P);
244 ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);
nouveau_nvkm_subdev_clk_mcp77.c 62 int N1, M1;
75 N1 = (coef & 0x0000ff00) >> 8;
78 clock = ref * N1 / M1;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 404 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
410 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
416 SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
424 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
426 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
435 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
437 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
526 SDValue N1);
528 SDValue N1);
530 SDValue N1, SDNodeFlags Flags)
    [all...]
SelectionDAG.cpp 1763 /// Swaps the values of N1 and N2. Swaps all indices in the shuffle mask M that
1764 /// point at N1 to point at N2 and indices that point at N2 to point at N1.
1765 static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef<int> M) {
1766 std::swap(N1, N2);
1770 SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1,
1774 assert(VT == N1.getValueType() && VT == N2.getValueType() &&
1778 if (N1.isUndef() && N2.isUndef())
1792 if (N1 == N2) {
1799 if (N1.isUndef()
    [all...]
TargetLowering.cpp 3028 SDValue N1, MutableArrayRef<int> Mask,
3032 std::swap(N0, N1);
3040 return DAG.getVectorShuffle(VT, DL, N0, N1, Mask);
3141 SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3147 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
3148 std::swap(N0, N1);
3156 if (N0.getOperand(0) == N1) {
3159 } else if (N0.getOperand(1) == N1) {
3211 EVT SCCVT, SDValue N0, SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI,
3215 if (!(C1 = dyn_cast<ConstantSDNode>(N1)))
    [all...]
  /src/regress/sys/fs/lfs/newfs_fsck/
mkfs_mount 24 mount -t lfs -o-N1 ${BVND}${MPART} ${TMPMP}
  /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/bios/
pll.h 11 uint8_t N1, M1, N2, M2;
13 uint8_t M1, N1, M2, N2;
  /src/sys/external/isc/libsodium/dist/test/default/
pwhash_scrypt_ll.c 7 static const uint64_t N1 = 16U;
54 tv(passwd1, salt1, N1, r1, p1);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/
nouveau_nvkm_subdev_devinit_nv50.c 46 int N1, M1, N2, M2, P;
55 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
65 nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
74 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);
78 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);
nouveau_nvkm_subdev_devinit_nv04.c 169 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
368 int N1, M1, N2, M2, P;
375 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
380 pv.N1 = N1;
  /src/external/apache2/llvm/dist/clang/include/clang/Tooling/ASTDiff/
ASTDiff.h 118 bool isMatchingAllowed(const Node &N1, const Node &N2) const {
119 return N1.getType().isSame(N2.getType());
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelDAGToDAG.cpp 116 bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
350 bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
352 if (N1.getOpcode() == ISD::LOAD &&
353 N1.hasOneUse() &&
354 IsLegalToFold(N1, Op, Op, OptLevel)) {
355 LoadSDNode *LD = cast<LoadSDNode>(N1);
361 MachineMemOperand *MemRef = cast<MemSDNode>(N1)->getMemOperand();
367 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
369 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/
nouveau_nvkm_subdev_fb_ramnv40.c 45 int N1, M1, N2, M2;
54 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
62 ram->coef = (N1 << 8) | M1;
65 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
nouveau_nvkm_subdev_fb_ramgf100.c 148 int N1, M1, P;
221 &N1, NULL, &M1, &P);
230 ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);
236 &N1, NULL, &M1, &P);
243 ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);
  /src/external/apache2/llvm/dist/clang/lib/Tooling/ASTDiff/
ASTDiff.cpp 758 const Node &N1 = T1.getNode(Id1);
760 if (N1.Children.size() != N2.Children.size() ||
764 for (size_t Id = 0, E = N1.Children.size(); Id < E; ++Id)
765 if (!identical(N1.Children[Id], N2.Children[Id]))
800 const Node &N1 = T1.getNode(Id1);
802 for (NodeId Src = Id1 + 1; Src <= N1.RightMostDescendant; ++Src) {
845 const Node &N1 = T1.getNode(Id1);
847 N1.Children, [&](NodeId Child) { return M.hasSrc(Child); });
945 Node &N1 = T1.getMutableNode(Id1);
952 N1.Change = N2.Change = Move
    [all...]
  /src/external/gpl3/gcc.old/dist/libgcc/
fixed-bit.h 1161 #define FRACT_TEMP(N1,N2) FIXED_CONVERT_OP(fract,N1,N2)
1162 #define FRACT2_TEMP(N1,N2) FIXED_CONVERT_OP2(fract,N1,N2)
1163 #define SATFRACT_TEMP(N1,N2) FIXED_CONVERT_OP(satfract,N1,N2)
1164 #define SATFRACT2_TEMP(N1,N2) FIXED_CONVERT_OP2(satfract,N1,N2)
1165 #define FRACTUNS_TEMP(N1,N2) FIXED_CONVERT_OP(fractuns,N1,N2
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 3507 SDValue N1 = Node->getOperand(1);
3511 if (N1 != N01 || !checkTwoUse(N1))
3513 if (!matchShiftAmt(N1, Bitwidth))
3644 SDValue N1 = Node->getOperand(1);
3670 ConstantSDNode *MaskCst = dyn_cast<ConstantSDNode>(N1);
3763 SDValue N1 = Node->getOperand(1);
3770 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
3772 N1.getOperand(0) };
3776 ReplaceUses(N1.getValue(1), SDValue(CNode, 2))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonCommonGEP.cpp 86 bool operator()(const GepNode *N1, const GepNode *N2) const {
87 auto F1 = Map.find(N1), F2 = Map.find(N2);
474 static NodePair node_pair(GepNode *N1, GepNode *N2) {
475 uintptr_t P1 = reinterpret_cast<uintptr_t>(N1);
478 return std::make_pair(N1, N2);
479 return std::make_pair(N2, N1);
490 static bool node_eq(GepNode *N1, GepNode *N2, NodePairSet &Eq,
494 if (node_hash(N1) != node_hash(N2))
497 NodePair NP = node_pair(N1, N2);
505 bool Root1 = N1->Flags & GepNode::Root
    [all...]
  /src/sys/arch/i386/stand/lib/
comio.S 27 # Initialize the serial port (dl) to 9600 baud, 8N1.
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 1355 SDValue N1 = N->getOperand(1);
1357 if (isZeroOrAllOnes(N1, AllOnes)) {
1364 OtherOp = N1;
1446 SDValue N1 = N->getOperand(1);
1448 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1450 if (N1.getNode()->hasOneUse())
1451 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1460 SDValue N1 = N->getOperand(1);
1463 if (N1.getNode()->hasOneUse())
1464 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false)
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
SelectionDAG.h 783 SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
981 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
983 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
990 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
992 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
994 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
996 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1003 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
1005 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
1007 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 584 SDValue N1 = Op.getOperand(1);
589 OtherOp = N1;
590 } else if (N1.getOpcode() == ISD::ADD) {
591 AddOp = N1;
1635 SDValue N1 = N->getOperand(1);
1638 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1643 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1671 SDValue N1 = N->getOperand(1);
1674 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1708 SDValue N1 = N->getOperand(1)
    [all...]

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