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Searched
refs:N10
(Results
1 - 4
of
4
) sorted by relevancy
/src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp
2392
SDValue
N10
= N1.getOperand(0);
2395
if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(
N10
))
2397
DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00,
N10
),
3555
// sub N0, (lshr
N10
, width-1) --> add N0, (ashr
N10
, width-1)
4331
SDValue
N10
= N1.getOperand(0);
4332
if (isConstantOrConstantVector(
N10
, /*NoOpaques*/ true) &&
4333
DAG.isKnownToBeAPowerOfTwo(
N10
)) {
4334
SDValue LogBase2 = BuildLogBase2(
N10
, DL);
6014
SDValue
N10
= N1->getOperand(0)
[
all
...]
/src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp
[
all
...]
/src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp
13060
SDValue
N10
= N1->getOperand(0);
13063
if (N00VT ==
N10
.getValueType() &&
13074
DAG.getNode(ISD::BITCAST, dl, MidVT,
N10
), Mask));
13099
SDValue
N10
= N1->getOperand(0);
13103
EVT N10VT =
N10
.getValueType();
13107
N10
->getOpcode() == ISD::EXTRACT_SUBVECTOR &&
13111
SDValue N10Source =
N10
->getOperand(0);
13120
uint64_t N10Index =
N10
.getConstantOperandVal(1);
/src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp
11941
SDValue
N10
= N1.getOperand(0);
11944
if (!IsVUZPShuffleNode(N00.getNode()) || N00.getNode() !=
N10
.getNode() ||
11945
N00 ==
N10
)
Completed in 79 milliseconds
Indexes created Wed Jun 10 00:26:05 UTC 2026