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    Searched refs:NumVecs (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 199 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
202 /// For NumVecs <= 2, QOpcodes1 is not used.
203 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
207 /// SelectVST - Select NEON store intrinsics. NumVecs should
210 /// For NumVecs <= 2, QOpcodes1 is not used.
211 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
215 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
219 unsigned NumVecs, const uint16_t *DOpcodes,
271 /// SelectMVE_VLD - Select MVE interleaving load intrinsics. NumVecs
274 /// pointer points to a set of NumVecs sub-opcodes used for th
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ARMISelLowering.cpp 14634 unsigned NumVecs = 0;
14640 NumVecs = 1; break;
14642 NumVecs = 2; break;
14644 NumVecs = 3; break;
14646 NumVecs = 4; break;
14657 NumVecs = 2; isLaneOp = true; break;
14659 NumVecs = 3; isLaneOp = true; break;
14661 NumVecs = 4; isLaneOp = true; break;
14663 NumVecs = 1; isLoadOp = false; break;
14665 NumVecs = 2; isLoadOp = false; break
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 241 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
248 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
250 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
252 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
253 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
254 void SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale,
268 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
269 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
270 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
271 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc)
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AArch64ISelLowering.cpp 10782 template <unsigned NumVecs>
10792 for (unsigned I = 0; I < NumVecs; ++I)
10796 // memVT is `NumVecs * VT`.
10798 EC * NumVecs);
14850 unsigned NumVecs = 0;
14855 NumVecs = 2; break;
14857 NumVecs = 3; break;
14859 NumVecs = 4; break;
14861 NumVecs = 2; IsStore = true; break;
14863 NumVecs = 3; IsStore = true; break
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  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
VectorUtils.cpp 786 unsigned NumVecs) {
789 for (unsigned j = 0; j < NumVecs; j++)
844 unsigned NumVecs = Vecs.size();
845 assert(NumVecs > 1 && "Should be at least two vectors");
851 for (unsigned i = 0; i < NumVecs - 1; i += 2) {
853 assert((V0->getType() == V1->getType() || i == NumVecs - 2) &&
860 if (NumVecs % 2 != 0)
861 TmpList.push_back(ResList[NumVecs - 1]);
864 NumVecs = ResList.size();
865 } while (NumVecs > 1)
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  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
VectorUtils.h 493 /// This function creates a shuffle mask for interleaving \p NumVecs vectors of
497 /// <0, VF, VF * 2, ..., VF * (NumVecs - 1), 1, VF + 1, VF * 2 + 1, ...>
499 /// For example, the mask for VF = 4 and NumVecs = 2 is:
502 llvm::SmallVector<int, 16> createInterleaveMask(unsigned VF, unsigned NumVecs);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 10310 int NumVecs = 2;
10313 NumVecs = 4;
10317 for (int VecNo = 0; VecNo < NumVecs; VecNo++) {
10320 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo
10560 unsigned NumVecs = VT.getSizeInBits() / 128;
10561 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) {
10605 unsigned NumVecs = 2;
10608 NumVecs = 4;
10610 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) {
10611 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx
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  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGBuiltin.cpp 15363 unsigned NumVecs = 2;
15366 NumVecs = 4;
15375 for (unsigned i=0; i<NumVecs; i++) {

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