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    Searched refs:PSL_RI (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/arch/powerpc/include/
psl.h 72 #define PSL_RI 0x00000002 /* ..6. recoverable interrupt */
75 #define PSL_601_MASK ~(PSL_VEC|PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE)
  /src/sys/arch/powerpc/powerpc/
clock.c 123 : "=r"(msr) : "K"(PSL_EE|PSL_RI));
rtas.c 237 PSL_FE1 | PSL_IR | PSL_DR | PSL_RI));
trap_subr.S 898 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
993 andi. %r6,%r6,(PSL_EE|PSL_ME|PSL_RI)@l
1058 ori %r7,%r7,(PSL_EE|PSL_ME|PSL_RI)@l
1132 ori %r6,%r6,PSL_RI; /* turn on recovery interrupt */\
1152 andi. %r3,%r3,~(PSL_EE|PSL_ME|PSL_RI)@l
openfirm.c 67 mtmsr(s & ~(PSL_EE|PSL_RI)); /* disable interrupts */
  /src/sys/arch/evbppc/nintendo/
machdep.c 476 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
  /src/sys/arch/powerpc/oea/
oea_machdep.c 444 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI;
470 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
ofwoea_machdep.c 272 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
cpu_subr.c 1663 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI;

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