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    Searched refs:R10 (Results 1 - 25 of 62) sorted by relevancy

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  /src/sys/external/bsd/gnu-efi/dist/inc/arm/
efisetjmp_arch.h 16 UINT32 R10;
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430RegisterInfo.cpp 43 MSP430::R8, MSP430::R9, MSP430::R10,
48 MSP430::R8, MSP430::R9, MSP430::R10,
53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCCallingConv.cpp 38 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 };
  /src/external/bsd/pcc/dist/pcc/arch/vax/
macdefs.h 136 # define R10 10
225 { R9, R10, XR8, XR10, -1 }, \
226 { R10, R11, XR9, -1 },
  /src/sys/arch/amd64/include/
frame_regs.h 27 * stubs copy %rcx to %r10).
35 greg(r10, R10, 6) /* tf_r10 */ \
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/
LanaiBaseInfo.h 66 case Lanai::R10:
  /src/external/bsd/pcc/dist/pcc/arch/arm/
macdefs.h 126 #define R10 10
133 #define SL R10
199 { R9, R10, R8R9, -1 }, \
  /src/external/bsd/pcc/dist/pcc/arch/pdp10/
macdefs.h 169 #define R10 010
228 { R7, R10, XR6, XR10, -1 }, \
229 { R10, R11, XR7, XR11, -1 }, \
  /src/external/gpl3/gcc.old/dist/libgcc/config/rl78/
fpbit-sf.S 36 movw r10, ax
285 movw r10, #0x7fff
289 mov r10, #0x8000
292 ;; Load the value into r10:r11:X:A
294 movw r10, ax
311 subw ax, r10
312 movw r10, ax
318 movw r10,#0x0
335 movw r10, ax
342 ;; Input in (lsb) r10.r11.x.a (msb)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFRegisterInfo.cpp 125 return BPF::R10;
  /src/external/gpl3/gcc.old/dist/libgcc/config/msp430/
epilogue.S 46 POP R10
lib2hw_mul.S 214 ;* - Operand 1 is in R8, R9, R10, R11
220 ;* R12:R15 = (R8:R9 * R12:R13) + ((R8:R9 * R14:R15) << 32) + ((R10:R11 * R12:R13) << 32)
228 ;* Registers used: R6, R7, R8, R9, R10, R11, R12, R13, R14, R15
233 PUSHM.A #5, R10
235 PUSHM.W #5, R10
237 PUSH R10 { PUSH R9 { PUSH R8 { PUSH R7 { PUSH R6
248 MOV.W R10, &\MPY32_LO
270 POPM.A #5, R10
272 POPM.W #5, R10
274 POP R6 { POP R7 { POP R8 { POP R9 { POP R10
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.h 54 case R8: case R9: case R10: case R11: case R12:
66 case R8: case R9: case R10: case R11: case R12:
ARMSLSHardening.cpp 144 {"__llvm_slsblr_thunk_arm_r10", ARM::R10, false},
158 {"__llvm_slsblr_thunk_thumb_r10", ARM::R10, true},
  /src/external/bsd/pcc/dist/pcc/arch/powerpc/
macdefs.h 157 #define R10 10 /* scratch register / argument 7 */
244 SAREG|TEMPREG, /* R10 */ \
322 { R9, R10, R8R9, -1 }, \
order.c 385 static int r[] = { R10, R9, R8, R7, R6, R5, R4, R3, R30, R31, -1 };
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreRegisterInfo.cpp 215 XCore::R8, XCore::R9, XCore::R10,
238 Reserved.set(XCore::R10);
322 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
  /src/external/bsd/pcc/dist/pcc/arch/hppa/
macdefs.h 127 #define R10 10
167 #define RD16 48 /* r10:r9 */
168 #define RD17 49 /* r11:r10 */
363 { R10, R9, -1 }, \
364 { R11, R10, -1 }, \
  /src/sys/arch/vax/include/
asm.h 46 #define R10 0x400
  /src/external/gpl3/gcc.old/dist/libgcc/config/avr/libf7/
asm-defs.h 106 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \
122 R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, \
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCTargetDesc.cpp 164 {codeview::RegisterId::R10, X86::R10},
659 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
696 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
732 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
768 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
769 return X86::R10;
  /src/sys/external/bsd/gnu-efi/dist/inc/
efidebug.h 285 UINT64 R10;
338 UINT64 R10;
499 UINT32 R10;
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/Disassembler/
BPFDisassembler.cpp 98 BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11};
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiRegisterInfo.cpp 54 Reserved.set(Lanai::R10);
  /src/external/bsd/pcc/dist/pcc/arch/amd64/
macdefs.h 168 #define R10 012

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