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    Searched refs:RLC_CNTL (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_si.c 5216 orig = data = RREG32(RLC_CNTL);
5220 WREG32(RLC_CNTL, data);
5232 tmp = RREG32(RLC_CNTL);
5234 WREG32(RLC_CNTL, rlc);
5828 WREG32(RLC_CNTL, 0);
5837 WREG32(RLC_CNTL, RLC_ENABLE);
radeon_r600.c 1738 WREG32(RLC_CNTL, 0);
1870 WREG32(RLC_CNTL, 0);
3579 WREG32(RLC_CNTL, 0);
3584 WREG32(RLC_CNTL, RLC_ENABLE);
radeon_cik.c 5838 tmp = RREG32(RLC_CNTL);
5840 WREG32(RLC_CNTL, rlc);
5847 orig = data = RREG32(RLC_CNTL);
5853 WREG32(RLC_CNTL, data);
5905 WREG32(RLC_CNTL, 0);
5921 WREG32(RLC_CNTL, RLC_ENABLE);
cikd.h 1395 #define RLC_CNTL 0xC300
sid.h 1302 #define RLC_CNTL 0xC300
evergreend.h 386 #define RLC_CNTL 0x3f00
r600d.h 687 #define RLC_CNTL 0x3f00
radeon_evergreen.c 4383 WREG32(RLC_CNTL, mask);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c 1806 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1847 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4006 uint32_t rlc_cntl; local in function:gfx_v10_0_is_rlc_enabled
4009 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4010 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
sid.h 1331 #define RLC_CNTL 0x30C0
amdgpu_gfx_v8_0.c 4079 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
4096 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
amdgpu_gfx_v9_0.c 2926 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2945 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

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