| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.h | 30 // parity(Rd) == parity(Ra).
32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
|
| AArch64PBQPRegAlloc.cpp | 158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd,
160 if (Rd == Ra)
165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) {
166 LLVM_DEBUG(dbgs() << "Rd is a physical reg:"
167 << Register::isPhysicalRegister(Rd) << '\n');
173 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
186 const LiveInterval &ld = LIs.getInterval(Rd);
242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd,
248 if (Rd != Ra) {
250 << " to " << printReg(Rd, TRI) << '\n';)
[all...] |
| /src/sys/arch/aarch64/aarch64/ |
| disasm.c | 800 uint64_t Rn, uint64_t Rd,
805 if ((z_op != NULL) && (Rd == 31)) {
808 PRINTF("%s\t%s, ", op, SREGNAME(sf, Rd));
813 if ((Rd == 31) || (Rn == 31)) {
843 uint64_t Rn, uint64_t Rd,
854 ZREGNAME(sf, Rd),
856 } else if ((znm_op != NULL) && (Rd == 31)) {
864 ZREGNAME(sf, Rd),
1032 uint64_t sf, uint64_t shift, uint64_t imm12, uint64_t Rn, uint64_t Rd,
1040 if (Rd == 31)
[all...] |
| trap.c | 683 int Rn, Rd, Rm, error;
686 Rd = __SHIFTOUT(insn, 0x0000f000);
710 tf->tf_reg[Rd] = val;
783 * mcr p15, 0, <Rd>, c7, c5, 4
792 * mcr p15, 0, <Rd>, c7, c10, 4
801 * mcr p15, 0, <Rd>, c7, c10, 5
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 889 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
894 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
897 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
980 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1008 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1029 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1042 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1054 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1059 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1584 unsigned Rd = fieldFromInstruction(insn, 0, 5)
[all...] |
| /src/sys/external/bsd/compiler_rt/dist/lib/xray/ |
| xray_mips.cc | 48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
|
| xray_mips64.cc | 28 PO_DSLL = 0x00000038, // dsll rd, rt, sa
49 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
51 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 2010 // For {LD,ST}RD, Rt must be even, else undefined.
2217 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2225 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2443 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2452 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2454 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2467 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2475 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2478 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2494 unsigned Rd = fieldFromInstruction(Insn, 16, 4)
[all...] |
| /src/external/gpl3/binutils/dist/include/opcode/ |
| ft32.h | 290 unsigned int Rd = (op32 >> 20) & 31;
298 if (Rd == R1)
304 r = Rd;
308 if ((find == NULL) && (Rd == R2))
314 r = Rd;
334 r = Rd;
|
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| ft32.h | 290 unsigned int Rd = (op32 >> 20) & 31;
298 if (Rd == R1)
304 r = Rd;
308 if ((find == NULL) && (Rd == R2))
314 r = Rd;
334 r = Rd;
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| aarch64-tbl.h | 544 the 3rd qualifier is used to help the encoding. */
3691 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3692 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3693 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3694 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3695 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3696 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3699 CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
3702 CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
3707 CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF)
[all...] |
| i386-dis-evex-w.h | 384 { "vpbroadcastb", { XM, Rd }, PREFIX_DATA },
388 { "vpbroadcastw", { XM, Rd }, PREFIX_DATA },
|
| i386-dis.c | 571 #define Rd { OP_R, d_mode }
2698 "{rd-",
3839 { "encodekey128", { Gd, Rd }, 0 },
3845 { "encodekey256", { Gd, Rd }, 0 },
14038 /* This must be the 3rd operand. */
14075 /* This must be the 3rd operand. */
14187 /* Swap 2nd and 3rd operands. */
14220 /* Swap 3rd and 4th operands. */
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| aarch64-tbl.h | 544 the 3rd qualifier is used to help the encoding. */
3471 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3472 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3473 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3474 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3475 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3476 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF),
3479 CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
3482 CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_HAS_ALIAS | F_SF),
3487 CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_ARITH_ADD | F_HAS_ALIAS | F_SF)
[all...] |
| i386-dis-evex-w.h | 384 { "vpbroadcastb", { XM, Rd }, PREFIX_DATA },
388 { "vpbroadcastw", { XM, Rd }, PREFIX_DATA },
|
| i386-dis.c | 571 #define Rd { OP_R, d_mode }
2689 "{rd-",
3830 { "encodekey128", { Gd, Rd }, 0 },
3836 { "encodekey256", { Gd, Rd }, 0 },
13999 /* This must be the 3rd operand. */
14036 /* This must be the 3rd operand. */
14148 /* Swap 2nd and 3rd operands. */
14181 /* Swap 3rd and 4th operands. */
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonConstExtenders.cpp | 323 Register Rd;
394 OffsetRange getOffsetRange(Register Rd) const;
497 if (ED.Rd.Reg != 0)
498 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
1125 // Get the allowable deviation from the current value of Rd by checking
1126 // all uses of Rd.
1127 OffsetRange HCE::getOffsetRange(Register Rd) const {
1129 for (const MachineOperand &Op : MRI->use_operands(Rd.Reg)) {
1133 if (Rd != Register(Op)
[all...] |
| HexagonFrameLowering.cpp | 143 // Rd = PS_alloca Rs, A
145 // Rd - address of the allocated space
2541 // Rd = alloca Rs, #A
2543 // If Rs and Rd are different registers, use this sequence:
2544 // Rd = sub(r29, Rs)
2546 // Rd = and(Rd, #-A) ; if necessary
2548 // Rd = add(Rd, #CF) ; CF size aligned to at most A
2550 // Rd = sub(r29, Rs
[all...] |
| HexagonInstrInfo.cpp | 1258 Register Rd = Op0.getReg();
1266 if (Rd != Rs)
1267 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1268 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1270 if (Rd != Rt)
1271 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
3364 // Rd = Rs
3371 // Rd = #u6
3401 // Rd=#U6 ; jump #r9:2
3402 // Rd=Rs ; jump #r9:
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-arm.c | 6714 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6749 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6850 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6868 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
7957 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
9170 /* This is a pseudo-op of the form "adr rd, label" to be converted
9171 into a relative address of the form "add rd, pc, #label-.-8". */
9176 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9192 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9194 add rd, pc, #low(label-.-8)
27497 unsigned int rd; local
28694 int rd = (newval >> 4) & 0xf; local
28893 int rd, rs; local
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-arm.c | 6717 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6752 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6853 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6871 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
7960 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
9173 /* This is a pseudo-op of the form "adr rd, label" to be converted
9174 into a relative address of the form "add rd, pc, #label-.-8". */
9179 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
9195 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9197 add rd, pc, #low(label-.-8)
27500 unsigned int rd; local
28697 int rd = (newval >> 4) & 0xf; local
28896 int rd, rs; local
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/ |
| RISCVDisassembler.cpp | 396 unsigned Rd = fieldFromInstruction(Insn, 7, 5);
398 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
406 unsigned Rd = fieldFromInstruction(Insn, 7, 5);
408 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/Disassembler/ |
| MSP430Disassembler.cpp | 194 unsigned Rd = fieldFromInstruction(Insn, 0, 4);
196 switch (Rd) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 730 // accept a 3rd argument, AccessAlignment which indicates the smallest
1692 MCOperand &Rd = Inst.getOperand(0);
1709 TmpInst.addOperand(Rd);
1723 if (Value == 0) { // convert to $Rd = $Rs
1725 MCOperand &Rd = Inst.getOperand(0);
1727 TmpInst.addOperand(Rd);
1735 MCOperand &Rd = Inst.getOperand(0);
1737 TmpInst.addOperand(Rd);
1923 MCOperand &Rd = Inst.getOperand(0);
1926 TmpInst.addOperand(Rd);
[all...] |
